author: Tom <support@vamrs.com> 2021-02-13 22:25:17 +0800
committer: Fu Wei <fu.wei@linaro.org> 2021-02-25 03:46:58 +0800
commit: b18e74b0e226dbfde83fc9586b34440691c60a53
parent: 5c6643d53e83133f9f5136d0b5739344e53854fa
Commit Summary:
Diffstat:
3 files changed, 49 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 6f432d2a5ceb..ac52165e6d2d 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -273,6 +273,44 @@ static int plic_starting_cpu(unsigned int cpu)
return 0;
}
+#if IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+#ifdef CONFIG_SOC_STARFIVE_VIC7100
+#define SIFIVE_L2_MAX_ECCINTR 4
+#else
+#define SIFIVE_L2_MAX_ECCINTR 3
+#endif
+static const struct of_device_id sifive_l2_ids[] = {
+ { .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "starfive,ccache0" },
+ { /* end of table */ },
+};
+
+static void sifive_l2_irq_disable(struct plic_handler *handler)
+{
+ int i, irq;
+ struct of_phandle_args oirq;
+
+ struct device_node *np = of_find_matching_node(NULL, sifive_l2_ids);
+ if (!np) {
+ pr_err("Can't get L2 cache device node.\n");
+ return;
+ }
+
+ for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
+ if (!of_irq_parse_one(np, i, &oirq)) {
+ irq = *oirq.args;
+ if (irq) {
+ pr_info("disable L2 cache irq %d in plic\n", irq);
+ plic_toggle(handler, irq, 0);
+ continue;
+ }
+ }
+ pr_err("Can't get L2 cache irq(#%d).\n", i);
+ }
+}
+#endif
+
+
static int __init plic_init(struct device_node *node,
struct device_node *parent)
{
@@ -366,6 +404,9 @@ static int __init plic_init(struct device_node *node,
done:
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
plic_toggle(handler, hwirq, 0);
+#if IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+ sifive_l2_irq_disable(handler);
+#endif
nr_handlers++;
}
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 4d0fdab56e81..4cccaad9e943 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -22,4 +22,8 @@ config SIFIVE_L2_FLUSH_SIZE
endif # SIFIVE_L2_FLUSH
+config SIFIVE_L2_IRQ_DISABLE
+ bool "Disable Level 2 Cache Controller interrupts"
+ default y if SOC_STARFIVE_VIC7100
+
endif
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 8ee8f8598b80..33b8e064579d 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -44,7 +44,9 @@
#define SIFIVE_L2_FLUSH64_LINE_LEN 64
static void __iomem *l2_base = NULL;
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
+#endif
static struct riscv_cacheinfo_ops l2_cache_ops;
enum {
@@ -195,6 +197,7 @@ static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_le
return NULL;
}
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
static irqreturn_t l2_int_handler(int irq, void *device)
{
unsigned int add_h, add_l;
@@ -240,12 +243,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
return IRQ_HANDLED;
}
+#endif
static int __init sifive_l2_init(void)
{
struct device_node *np;
struct resource res;
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
int i, rc;
+#endif
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -258,6 +264,7 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
g_irq[i] = irq_of_parse_and_map(np, i);
rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
@@ -266,6 +273,7 @@ static int __init sifive_l2_init(void)
return rc;
}
}
+#endif
l2_config_read();