fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 2) * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 3) * 370/XP, Dove, Orion5x and MV78xx0)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 4) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 5) * This file is licensed under the terms of the GNU General Public
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 6) * License version 2. This program is licensed "as is" without any
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 7) * warranty of any kind, whether express or implied.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 8) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 9) * The Marvell EBU SoCs have a configurable physical address space:
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 10) * the physical address at which certain devices (PCIe, NOR, NAND,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 11) * etc.) sit can be configured. The configuration takes place through
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 12) * two sets of registers:
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 13) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 14) * - One to configure the access of the CPU to the devices. Depending
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 15) * on the families, there are between 8 and 20 configurable windows,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 16) * each can be use to create a physical memory window that maps to a
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 17) * specific device. Devices are identified by a tuple (target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 18) * attribute).
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 19) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 20) * - One to configure the access to the CPU to the SDRAM. There are
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 21) * either 2 (for Dove) or 4 (for other families) windows to map the
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 22) * SDRAM into the physical address space.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 23) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 24) * This driver:
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 25) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 26) * - Reads out the SDRAM address decoding windows at initialization
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 27) * time, and fills the mvebu_mbus_dram_info structure with these
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 28) * informations. The exported function mv_mbus_dram_info() allow
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 29) * device drivers to get those informations related to the SDRAM
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 30) * address decoding windows. This is because devices also have their
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 31) * own windows (configured through registers that are part of each
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 32) * device register space), and therefore the drivers for Marvell
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 33) * devices have to configure those device -> SDRAM windows to ensure
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 34) * that DMA works properly.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 35) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 36) * - Provides an API for platform code or device drivers to
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 37) * dynamically add or remove address decoding windows for the CPU ->
6275afef74d8b (Thomas Petazzoni 2013-07-26 10:17:52 -0300 38) * device accesses. This API is mvebu_mbus_add_window_by_id(),
6275afef74d8b (Thomas Petazzoni 2013-07-26 10:17:52 -0300 39) * mvebu_mbus_add_window_remap_by_id() and
6275afef74d8b (Thomas Petazzoni 2013-07-26 10:17:52 -0300 40) * mvebu_mbus_del_window().
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 41) *
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 42) * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 43) * see the list of CPU -> SDRAM windows and their configuration
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 44) * (file 'sdram') and the list of CPU -> devices windows and their
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 45) * configuration (file 'devices').
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 46) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 47)
b15d0b5256056 (Ezequiel Garcia 2013-06-07 13:47:38 -0300 48) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
b15d0b5256056 (Ezequiel Garcia 2013-06-07 13:47:38 -0300 49)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 50) #include <linux/kernel.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 51) #include <linux/module.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 52) #include <linux/init.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 53) #include <linux/mbus.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 54) #include <linux/io.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 55) #include <linux/ioport.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 56) #include <linux/of.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 57) #include <linux/of_address.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 58) #include <linux/debugfs.h>
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 59) #include <linux/log2.h>
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 60) #include <linux/memblock.h>
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 61) #include <linux/syscore_ops.h>
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 62)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 63) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 64) * DDR target is the same on all platforms.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 65) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 66) #define TARGET_DDR 0
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 67)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 68) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 69) * CPU Address Decode Windows registers
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 70) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 71) #define WIN_CTRL_OFF 0x0000
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 72) #define WIN_CTRL_ENABLE BIT(0)
8c9e06e647686 (Nicolas Schichan 2015-05-28 10:40:12 +0200 73) /* Only on HW I/O coherency capable platforms */
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 74) #define WIN_CTRL_SYNCBARRIER BIT(1)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 75) #define WIN_CTRL_TGT_MASK 0xf0
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 76) #define WIN_CTRL_TGT_SHIFT 4
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 77) #define WIN_CTRL_ATTR_MASK 0xff00
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 78) #define WIN_CTRL_ATTR_SHIFT 8
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 79) #define WIN_CTRL_SIZE_MASK 0xffff0000
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 80) #define WIN_CTRL_SIZE_SHIFT 16
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 81) #define WIN_BASE_OFF 0x0004
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 82) #define WIN_BASE_LOW 0xffff0000
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 83) #define WIN_BASE_HIGH 0xf
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 84) #define WIN_REMAP_LO_OFF 0x0008
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 85) #define WIN_REMAP_LOW 0xffff0000
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 86) #define WIN_REMAP_HI_OFF 0x000c
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 87)
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 88) #define UNIT_SYNC_BARRIER_OFF 0x84
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 89) #define UNIT_SYNC_BARRIER_ALL 0xFFFF
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 90)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 91) #define ATTR_HW_COHERENCY (0x1 << 4)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 92)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 93) #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 94) #define DDR_BASE_CS_HIGH_MASK 0xf
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 95) #define DDR_BASE_CS_LOW_MASK 0xff000000
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 96) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 97) #define DDR_SIZE_ENABLED BIT(0)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 98) #define DDR_SIZE_CS_MASK 0x1c
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 99) #define DDR_SIZE_CS_SHIFT 2
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 100) #define DDR_SIZE_MASK 0xff000000
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 101)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 102) #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 103)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 104) /* Relative to mbusbridge_base */
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 105) #define MBUS_BRIDGE_CTRL_OFF 0x0
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 106) #define MBUS_BRIDGE_BASE_OFF 0x4
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 107)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 108) /* Maximum number of windows, for all known platforms */
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 109) #define MBUS_WINS_MAX 20
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 110)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 111) struct mvebu_mbus_state;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 112)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 113) struct mvebu_mbus_soc_data {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 114) unsigned int num_wins;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 115) bool has_mbus_bridge;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 116) unsigned int (*win_cfg_offset)(const int win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 117) unsigned int (*win_remap_offset)(const int win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 118) void (*setup_cpu_target)(struct mvebu_mbus_state *s);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 119) int (*save_cpu_target)(struct mvebu_mbus_state *s,
fce7b5ae1273a (Ben Dooks 2016-06-21 16:16:18 +0100 120) u32 __iomem *store_addr);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 121) int (*show_cpu_target)(struct mvebu_mbus_state *s,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 122) struct seq_file *seq, void *v);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 123) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 124)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 125) /*
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 126) * Used to store the state of one MBus window accross suspend/resume.
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 127) */
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 128) struct mvebu_mbus_win_data {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 129) u32 ctrl;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 130) u32 base;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 131) u32 remap_lo;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 132) u32 remap_hi;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 133) };
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 134)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 135) struct mvebu_mbus_state {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 136) void __iomem *mbuswins_base;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 137) void __iomem *sdramwins_base;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 138) void __iomem *mbusbridge_base;
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 139) phys_addr_t sdramwins_phys_base;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 140) struct dentry *debugfs_root;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 141) struct dentry *debugfs_sdram;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 142) struct dentry *debugfs_devs;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 143) struct resource pcie_mem_aperture;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 144) struct resource pcie_io_aperture;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 145) const struct mvebu_mbus_soc_data *soc;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 146) int hw_io_coherency;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 147)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 148) /* Used during suspend/resume */
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 149) u32 mbus_bridge_ctrl;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 150) u32 mbus_bridge_base;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 151) struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 152) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 153)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 154) static struct mvebu_mbus_state mbus_state;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 155)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 156) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 157) * We provide two variants of the mv_mbus_dram_info() function:
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 158) *
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 159) * - The normal one, where the described DRAM ranges may overlap with
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 160) * the I/O windows, but for which the DRAM ranges are guaranteed to
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 161) * have a power of two size. Such ranges are suitable for the DMA
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 162) * masters that only DMA between the RAM and the device, which is
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 163) * actually all devices except the crypto engines.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 164) *
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 165) * - The 'nooverlap' one, where the described DRAM ranges are
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 166) * guaranteed to not overlap with the I/O windows, but for which the
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 167) * DRAM ranges will not have power of two sizes. They will only be
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 168) * aligned on a 64 KB boundary, and have a size multiple of 64
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 169) * KB. Such ranges are suitable for the DMA masters that DMA between
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 170) * the crypto SRAM (which is mapped through an I/O window) and a
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 171) * device. This is the case for the crypto engines.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 172) */
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 173)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 174) static struct mbus_dram_target_info mvebu_mbus_dram_info;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 175) static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 176)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 177) const struct mbus_dram_target_info *mv_mbus_dram_info(void)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 178) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 179) return &mvebu_mbus_dram_info;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 180) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 181) EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 182)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 183) const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 184) {
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 185) return &mvebu_mbus_dram_info_nooverlap;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 186) }
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 187) EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 188)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 189) /* Checks whether the given window has remap capability */
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 190) static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 191) const int win)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 192) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 193) return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 194) }
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 195)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 196) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 197) * Functions to manipulate the address decoding windows
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 198) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 199)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 200) static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 201) int win, int *enabled, u64 *base,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 202) u32 *size, u8 *target, u8 *attr,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 203) u64 *remap)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 204) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 205) void __iomem *addr = mbus->mbuswins_base +
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 206) mbus->soc->win_cfg_offset(win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 207) u32 basereg = readl(addr + WIN_BASE_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 208) u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 209)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 210) if (!(ctrlreg & WIN_CTRL_ENABLE)) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 211) *enabled = 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 212) return;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 213) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 214)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 215) *enabled = 1;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 216) *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 217) *base |= (basereg & WIN_BASE_LOW);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 218) *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 219)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 220) if (target)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 221) *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 222)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 223) if (attr)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 224) *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 225)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 226) if (remap) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 227) if (mvebu_mbus_window_is_remappable(mbus, win)) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 228) u32 remap_low, remap_hi;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 229) void __iomem *addr_rmp = mbus->mbuswins_base +
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 230) mbus->soc->win_remap_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 231) remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 232) remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 233) *remap = ((u64)remap_hi << 32) | remap_low;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 234) } else
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 235) *remap = 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 236) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 237) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 238)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 239) static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 240) int win)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 241) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 242) void __iomem *addr;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 243)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 244) addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 245) writel(0, addr + WIN_BASE_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 246) writel(0, addr + WIN_CTRL_OFF);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 247)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 248) if (mvebu_mbus_window_is_remappable(mbus, win)) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 249) addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 250) writel(0, addr + WIN_REMAP_LO_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 251) writel(0, addr + WIN_REMAP_HI_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 252) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 253) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 254)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 255) /* Checks whether the given window number is available */
38bdf45f4aa5c (Andrew Lunn 2015-01-18 09:46:10 -0600 256)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 257) static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 258) const int win)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 259) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 260) void __iomem *addr = mbus->mbuswins_base +
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 261) mbus->soc->win_cfg_offset(win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 262) u32 ctrl = readl(addr + WIN_CTRL_OFF);
38bdf45f4aa5c (Andrew Lunn 2015-01-18 09:46:10 -0600 263)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 264) return !(ctrl & WIN_CTRL_ENABLE);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 265) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 266)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 267) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 268) * Checks whether the given (base, base+size) area doesn't overlap an
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 269) * existing region
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 270) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 271) static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 272) phys_addr_t base, size_t size,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 273) u8 target, u8 attr)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 274) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 275) u64 end = (u64)base + size;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 276) int win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 277)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 278) for (win = 0; win < mbus->soc->num_wins; win++) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 279) u64 wbase, wend;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 280) u32 wsize;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 281) u8 wtarget, wattr;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 282) int enabled;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 283)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 284) mvebu_mbus_read_window(mbus, win,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 285) &enabled, &wbase, &wsize,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 286) &wtarget, &wattr, NULL);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 287)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 288) if (!enabled)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 289) continue;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 290)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 291) wend = wbase + wsize;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 292)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 293) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 294) * Check if the current window overlaps with the
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 295) * proposed physical range
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 296) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 297) if ((u64)base < wend && end > wbase)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 298) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 299) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 300)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 301) return 1;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 302) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 303)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 304) static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 305) phys_addr_t base, size_t size)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 306) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 307) int win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 308)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 309) for (win = 0; win < mbus->soc->num_wins; win++) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 310) u64 wbase;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 311) u32 wsize;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 312) int enabled;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 313)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 314) mvebu_mbus_read_window(mbus, win,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 315) &enabled, &wbase, &wsize,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 316) NULL, NULL, NULL);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 317)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 318) if (!enabled)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 319) continue;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 320)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 321) if (base == wbase && size == wsize)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 322) return win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 323) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 324)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 325) return -ENODEV;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 326) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 327)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 328) static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 329) int win, phys_addr_t base, size_t size,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 330) phys_addr_t remap, u8 target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 331) u8 attr)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 332) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 333) void __iomem *addr = mbus->mbuswins_base +
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 334) mbus->soc->win_cfg_offset(win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 335) u32 ctrl, remap_addr;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 336)
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 337) if (!is_power_of_2(size)) {
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 338) WARN(true, "Invalid MBus window size: 0x%zx\n", size);
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 339) return -EINVAL;
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 340) }
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 341)
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 342) if ((base & (phys_addr_t)(size - 1)) != 0) {
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 343) WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 344) size);
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 345) return -EINVAL;
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 346) }
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 347)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 348) ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 349) (attr << WIN_CTRL_ATTR_SHIFT) |
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 350) (target << WIN_CTRL_TGT_SHIFT) |
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 351) WIN_CTRL_ENABLE;
8c9e06e647686 (Nicolas Schichan 2015-05-28 10:40:12 +0200 352) if (mbus->hw_io_coherency)
8c9e06e647686 (Nicolas Schichan 2015-05-28 10:40:12 +0200 353) ctrl |= WIN_CTRL_SYNCBARRIER;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 354)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 355) writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 356) writel(ctrl, addr + WIN_CTRL_OFF);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 357)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 358) if (mvebu_mbus_window_is_remappable(mbus, win)) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 359) void __iomem *addr_rmp = mbus->mbuswins_base +
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 360) mbus->soc->win_remap_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 361)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 362) if (remap == MVEBU_MBUS_NO_REMAP)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 363) remap_addr = base;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 364) else
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 365) remap_addr = remap;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 366) writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 367) writel(0, addr_rmp + WIN_REMAP_HI_OFF);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 368) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 369)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 370) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 371) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 372)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 373) static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 374) phys_addr_t base, size_t size,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 375) phys_addr_t remap, u8 target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 376) u8 attr)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 377) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 378) int win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 379)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 380) if (remap == MVEBU_MBUS_NO_REMAP) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 381) for (win = 0; win < mbus->soc->num_wins; win++) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 382) if (mvebu_mbus_window_is_remappable(mbus, win))
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 383) continue;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 384)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 385) if (mvebu_mbus_window_is_free(mbus, win))
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 386) return mvebu_mbus_setup_window(mbus, win, base,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 387) size, remap,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 388) target, attr);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 389) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 390) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 391)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 392) for (win = 0; win < mbus->soc->num_wins; win++) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 393) /* Skip window if need remap but is not supported */
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 394) if ((remap != MVEBU_MBUS_NO_REMAP) &&
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 395) !mvebu_mbus_window_is_remappable(mbus, win))
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 396) continue;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 397)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 398) if (mvebu_mbus_window_is_free(mbus, win))
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 399) return mvebu_mbus_setup_window(mbus, win, base, size,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 400) remap, target, attr);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 401) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 402)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 403) return -ENOMEM;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 404) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 405)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 406) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 407) * Debugfs debugging
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 408) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 409)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 410) /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 411) static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 412) struct seq_file *seq, void *v)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 413) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 414) int i;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 415)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 416) for (i = 0; i < 4; i++) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 417) u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 418) u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 419) u64 base;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 420) u32 size;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 421)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 422) if (!(sizereg & DDR_SIZE_ENABLED)) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 423) seq_printf(seq, "[%d] disabled\n", i);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 424) continue;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 425) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 426)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 427) base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 428) base |= basereg & DDR_BASE_CS_LOW_MASK;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 429) size = (sizereg | ~DDR_SIZE_MASK);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 430)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 431) seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 432) i, (unsigned long long)base,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 433) (unsigned long long)base + size + 1,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 434) (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 435) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 436)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 437) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 438) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 439)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 440) /* Special function for Dove */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 441) static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 442) struct seq_file *seq, void *v)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 443) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 444) int i;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 445)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 446) for (i = 0; i < 2; i++) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 447) u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 448) u64 base;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 449) u32 size;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 450)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 451) if (!(map & 1)) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 452) seq_printf(seq, "[%d] disabled\n", i);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 453) continue;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 454) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 455)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 456) base = map & 0xff800000;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 457) size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 458)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 459) seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 460) i, (unsigned long long)base,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 461) (unsigned long long)base + size, i);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 462) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 463)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 464) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 465) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 466)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 467) static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 468) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 469) struct mvebu_mbus_state *mbus = &mbus_state;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 470) return mbus->soc->show_cpu_target(mbus, seq, v);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 471) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 472)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 473) static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 474) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 475) return single_open(file, mvebu_sdram_debug_show, inode->i_private);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 476) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 477)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 478) static const struct file_operations mvebu_sdram_debug_fops = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 479) .open = mvebu_sdram_debug_open,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 480) .read = seq_read,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 481) .llseek = seq_lseek,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 482) .release = single_release,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 483) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 484)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 485) static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 486) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 487) struct mvebu_mbus_state *mbus = &mbus_state;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 488) int win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 489)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 490) for (win = 0; win < mbus->soc->num_wins; win++) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 491) u64 wbase, wremap;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 492) u32 wsize;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 493) u8 wtarget, wattr;
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 494) int enabled;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 495)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 496) mvebu_mbus_read_window(mbus, win,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 497) &enabled, &wbase, &wsize,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 498) &wtarget, &wattr, &wremap);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 499)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 500) if (!enabled) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 501) seq_printf(seq, "[%02d] disabled\n", win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 502) continue;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 503) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 504)
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 505) seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 506) win, (unsigned long long)wbase,
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 507) (unsigned long long)(wbase + wsize), wtarget, wattr);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 508)
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 509) if (!is_power_of_2(wsize) ||
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 510) ((wbase & (u64)(wsize - 1)) != 0))
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 511) seq_puts(seq, " (Invalid base/size!!)");
09752a12f430f (Jason Gunthorpe 2014-04-18 14:19:51 +0200 512)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 513) if (mvebu_mbus_window_is_remappable(mbus, win)) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 514) seq_printf(seq, " (remap %016llx)\n",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 515) (unsigned long long)wremap);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 516) } else
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 517) seq_printf(seq, "\n");
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 518) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 519)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 520) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 521) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 522)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 523) static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 524) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 525) return single_open(file, mvebu_devs_debug_show, inode->i_private);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 526) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 527)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 528) static const struct file_operations mvebu_devs_debug_fops = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 529) .open = mvebu_devs_debug_open,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 530) .read = seq_read,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 531) .llseek = seq_lseek,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 532) .release = single_release,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 533) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 534)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 535) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 536) * SoC-specific functions and definitions
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 537) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 538)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 539) static unsigned int generic_mbus_win_cfg_offset(int win)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 540) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 541) return win << 4;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 542) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 543)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 544) static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 545) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 546) /* The register layout is a bit annoying and the below code
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 547) * tries to cope with it.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 548) * - At offset 0x0, there are the registers for the first 8
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 549) * windows, with 4 registers of 32 bits per window (ctrl,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 550) * base, remap low, remap high)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 551) * - Then at offset 0x80, there is a hole of 0x10 bytes for
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 552) * the internal registers base address and internal units
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 553) * sync barrier register.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 554) * - Then at offset 0x90, there the registers for 12
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 555) * windows, with only 2 registers of 32 bits per window
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 556) * (ctrl, base).
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 557) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 558) if (win < 8)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 559) return win << 4;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 560) else
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 561) return 0x90 + ((win - 8) << 3);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 562) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 563)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 564) static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 565) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 566) if (win < 8)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 567) return win << 4;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 568) else
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 569) return 0x900 + ((win - 8) << 4);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 570) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 571)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 572) static unsigned int generic_mbus_win_remap_2_offset(int win)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 573) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 574) if (win < 2)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 575) return generic_mbus_win_cfg_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 576) else
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 577) return MVEBU_MBUS_NO_REMAP;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 578) }
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 579)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 580) static unsigned int generic_mbus_win_remap_4_offset(int win)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 581) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 582) if (win < 4)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 583) return generic_mbus_win_cfg_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 584) else
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 585) return MVEBU_MBUS_NO_REMAP;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 586) }
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 587)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 588) static unsigned int generic_mbus_win_remap_8_offset(int win)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 589) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 590) if (win < 8)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 591) return generic_mbus_win_cfg_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 592) else
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 593) return MVEBU_MBUS_NO_REMAP;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 594) }
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 595)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 596) static unsigned int armada_xp_mbus_win_remap_offset(int win)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 597) {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 598) if (win < 8)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 599) return generic_mbus_win_cfg_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 600) else if (win == 13)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 601) return 0xF0 - WIN_REMAP_LO_OFF;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 602) else
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 603) return MVEBU_MBUS_NO_REMAP;
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 604) }
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 605)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 606) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 607) * Use the memblock information to find the MBus bridge hole in the
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 608) * physical address space.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 609) */
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 610) static void __init
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 611) mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 612) {
b10d6bca87204 (Mike Rapoport 2020-10-13 16:58:08 -0700 613) phys_addr_t reg_start, reg_end;
b10d6bca87204 (Mike Rapoport 2020-10-13 16:58:08 -0700 614) uint64_t i, s = 0;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 615)
b10d6bca87204 (Mike Rapoport 2020-10-13 16:58:08 -0700 616) for_each_mem_range(i, ®_start, ®_end) {
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 617) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 618) * This part of the memory is above 4 GB, so we don't
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 619) * care for the MBus bridge hole.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 620) */
a2fa9e57a68cd (Arnd Bergmann 2021-03-23 14:19:42 +0100 621) if ((u64)reg_start >= 0x100000000ULL)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 622) continue;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 623)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 624) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 625) * The MBus bridge hole is at the end of the RAM under
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 626) * the 4 GB limit.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 627) */
b10d6bca87204 (Mike Rapoport 2020-10-13 16:58:08 -0700 628) if (reg_end > s)
b10d6bca87204 (Mike Rapoport 2020-10-13 16:58:08 -0700 629) s = reg_end;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 630) }
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 631)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 632) *start = s;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 633) *end = 0x100000000ULL;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 634) }
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 635)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 636) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 637) * This function fills in the mvebu_mbus_dram_info_nooverlap data
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 638) * structure, by looking at the mvebu_mbus_dram_info data, and
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 639) * removing the parts of it that overlap with I/O windows.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 640) */
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 641) static void __init
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 642) mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 643) {
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 644) uint64_t mbus_bridge_base, mbus_bridge_end;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 645) int cs_nooverlap = 0;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 646) int i;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 647)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 648) mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 649)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 650) for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 651) struct mbus_dram_window *w;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 652) u64 base, size, end;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 653)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 654) w = &mvebu_mbus_dram_info.cs[i];
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 655) base = w->base;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 656) size = w->size;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 657) end = base + size;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 658)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 659) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 660) * The CS is fully enclosed inside the MBus bridge
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 661) * area, so ignore it.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 662) */
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 663) if (base >= mbus_bridge_base && end <= mbus_bridge_end)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 664) continue;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 665)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 666) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 667) * Beginning of CS overlaps with end of MBus, raise CS
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 668) * base address, and shrink its size.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 669) */
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 670) if (base >= mbus_bridge_base && end > mbus_bridge_end) {
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 671) size -= mbus_bridge_end - base;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 672) base = mbus_bridge_end;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 673) }
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 674)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 675) /*
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 676) * End of CS overlaps with beginning of MBus, shrink
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 677) * CS size.
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 678) */
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 679) if (base < mbus_bridge_base && end > mbus_bridge_base)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 680) size -= end - mbus_bridge_base;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 681)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 682) w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 683) w->cs_index = i;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 684) w->mbus_attr = 0xf & ~(1 << i);
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 685) if (mbus->hw_io_coherency)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 686) w->mbus_attr |= ATTR_HW_COHERENCY;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 687) w->base = base;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 688) w->size = size;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 689) }
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 690)
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 691) mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 692) mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 693) }
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 694)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 695) static void __init
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 696) mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 697) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 698) int i;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 699) int cs;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 700)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 701) mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 702)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 703) for (i = 0, cs = 0; i < 4; i++) {
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 704) u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 705) u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
1737cac693693 (Thomas Petazzoni 2015-01-09 10:59:04 -0600 706)
1737cac693693 (Thomas Petazzoni 2015-01-09 10:59:04 -0600 707) /*
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 708) * We only take care of entries for which the chip
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 709) * select is enabled, and that don't have high base
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 710) * address bits set (devices can only access the first
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 711) * 32 bits of the memory).
1737cac693693 (Thomas Petazzoni 2015-01-09 10:59:04 -0600 712) */
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 713) if ((size & DDR_SIZE_ENABLED) &&
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 714) !(base & DDR_BASE_CS_HIGH_MASK)) {
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 715) struct mbus_dram_window *w;
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 716)
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 717) w = &mvebu_mbus_dram_info.cs[cs++];
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 718) w->cs_index = i;
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 719) w->mbus_attr = 0xf & ~(1 << i);
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 720) if (mbus->hw_io_coherency)
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 721) w->mbus_attr |= ATTR_HW_COHERENCY;
885dbd154b2f2 (Thomas Petazzoni 2015-05-28 10:40:13 +0200 722) w->base = base & DDR_BASE_CS_LOW_MASK;
2bbbd96357ce7 (Jan Luebbe 2017-08-28 17:25:16 +0200 723) w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 724) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 725) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 726) mvebu_mbus_dram_info.num_cs = cs;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 727) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 728)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 729) static int
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 730) mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
fce7b5ae1273a (Ben Dooks 2016-06-21 16:16:18 +0100 731) u32 __iomem *store_addr)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 732) {
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 733) int i;
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 734)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 735) for (i = 0; i < 4; i++) {
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 736) u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 737) u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 738)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 739) writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 740) store_addr++);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 741) writel(base, store_addr++);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 742) writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 743) store_addr++);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 744) writel(size, store_addr++);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 745) }
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 746)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 747) /* We've written 16 words to the store address */
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 748) return 16;
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 749) }
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 750)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 751) static void __init
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 752) mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 753) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 754) int i;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 755) int cs;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 756)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 757) mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 758)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 759) for (i = 0, cs = 0; i < 2; i++) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 760) u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 761)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 762) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 763) * Chip select enabled?
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 764) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 765) if (map & 1) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 766) struct mbus_dram_window *w;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 767)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 768) w = &mvebu_mbus_dram_info.cs[cs++];
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 769) w->cs_index = i;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 770) w->mbus_attr = 0; /* CS address decoding done inside */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 771) /* the DDR controller, no need to */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 772) /* provide attributes */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 773) w->base = map & 0xff800000;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 774) w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 775) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 776) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 777)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 778) mvebu_mbus_dram_info.num_cs = cs;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 779) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 780)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 781) static int
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 782) mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
fce7b5ae1273a (Ben Dooks 2016-06-21 16:16:18 +0100 783) u32 __iomem *store_addr)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 784) {
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 785) int i;
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 786)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 787) for (i = 0; i < 2; i++) {
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 788) u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 789)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 790) writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 791) store_addr++);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 792) writel(map, store_addr++);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 793) }
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 794)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 795) /* We've written 4 words to the store address */
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 796) return 4;
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 797) }
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 798)
fce7b5ae1273a (Ben Dooks 2016-06-21 16:16:18 +0100 799) int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 800) {
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 801) return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 802) }
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 803)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 804) static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 805) .num_wins = 20,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 806) .has_mbus_bridge = true,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 807) .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 808) .win_remap_offset = generic_mbus_win_remap_8_offset,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 809) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 810) .show_cpu_target = mvebu_sdram_debug_show_orion,
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 811) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 812) };
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 813)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 814) static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 815) .num_wins = 20,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 816) .has_mbus_bridge = true,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 817) .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 818) .win_remap_offset = armada_xp_mbus_win_remap_offset,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 819) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 820) .show_cpu_target = mvebu_sdram_debug_show_orion,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 821) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 822) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 823)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 824) static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 825) .num_wins = 8,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 826) .win_cfg_offset = generic_mbus_win_cfg_offset,
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 827) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 828) .win_remap_offset = generic_mbus_win_remap_4_offset,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 829) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 830) .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 831) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 832)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 833) static const struct mvebu_mbus_soc_data dove_mbus_data = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 834) .num_wins = 8,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 835) .win_cfg_offset = generic_mbus_win_cfg_offset,
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 836) .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 837) .win_remap_offset = generic_mbus_win_remap_4_offset,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 838) .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 839) .show_cpu_target = mvebu_sdram_debug_show_dove,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 840) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 841)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 842) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 843) * Some variants of Orion5x have 4 remappable windows, some other have
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 844) * only two of them.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 845) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 846) static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 847) .num_wins = 8,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 848) .win_cfg_offset = generic_mbus_win_cfg_offset,
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 849) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 850) .win_remap_offset = generic_mbus_win_remap_4_offset,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 851) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 852) .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 853) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 854)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 855) static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 856) .num_wins = 8,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 857) .win_cfg_offset = generic_mbus_win_cfg_offset,
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 858) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 859) .win_remap_offset = generic_mbus_win_remap_2_offset,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 860) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 861) .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 862) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 863)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 864) static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 865) .num_wins = 14,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 866) .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 867) .save_cpu_target = mvebu_mbus_default_save_cpu_target,
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 868) .win_remap_offset = generic_mbus_win_remap_8_offset,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 869) .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 870) .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 871) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 872)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 873) static const struct of_device_id of_mvebu_mbus_ids[] = {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 874) { .compatible = "marvell,armada370-mbus",
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 875) .data = &armada_370_mbus_data, },
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 876) { .compatible = "marvell,armada375-mbus",
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 877) .data = &armada_xp_mbus_data, },
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 878) { .compatible = "marvell,armada380-mbus",
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 879) .data = &armada_xp_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 880) { .compatible = "marvell,armadaxp-mbus",
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 881) .data = &armada_xp_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 882) { .compatible = "marvell,kirkwood-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 883) .data = &kirkwood_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 884) { .compatible = "marvell,dove-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 885) .data = &dove_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 886) { .compatible = "marvell,orion5x-88f5281-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 887) .data = &orion5x_4win_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 888) { .compatible = "marvell,orion5x-88f5182-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 889) .data = &orion5x_2win_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 890) { .compatible = "marvell,orion5x-88f5181-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 891) .data = &orion5x_2win_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 892) { .compatible = "marvell,orion5x-88f6183-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 893) .data = &orion5x_4win_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 894) { .compatible = "marvell,mv78xx0-mbus",
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 895) .data = &mv78xx0_mbus_data, },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 896) { },
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 897) };
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 898)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 899) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 900) * Public API of the driver
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 901) */
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 902) int mvebu_mbus_add_window_remap_by_id(unsigned int target,
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 903) unsigned int attribute,
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 904) phys_addr_t base, size_t size,
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 905) phys_addr_t remap)
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 906) {
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 907) struct mvebu_mbus_state *s = &mbus_state;
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 908)
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 909) if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 910) pr_err("cannot add window '%x:%x', conflicts with another window\n",
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 911) target, attribute);
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 912) return -EINVAL;
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 913) }
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 914)
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 915) return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 916) }
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 917)
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 918) int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 919) phys_addr_t base, size_t size)
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 920) {
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 921) return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 922) size, MVEBU_MBUS_NO_REMAP);
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 923) }
6a63b098f0ea3 (Thomas Petazzoni 2013-07-26 10:17:39 -0300 924)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 925) int mvebu_mbus_del_window(phys_addr_t base, size_t size)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 926) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 927) int win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 928)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 929) win = mvebu_mbus_find_window(&mbus_state, base, size);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 930) if (win < 0)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 931) return win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 932)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 933) mvebu_mbus_disable_window(&mbus_state, win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 934) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 935) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 936)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 937) void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 938) {
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 939) if (!res)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 940) return;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 941) *res = mbus_state.pcie_mem_aperture;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 942) }
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 943)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 944) void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 945) {
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 946) if (!res)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 947) return;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 948) *res = mbus_state.pcie_io_aperture;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 949) }
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 950)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 951) int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 952) {
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 953) const struct mbus_dram_target_info *dram;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 954) int i;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 955)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 956) /* Get dram info */
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 957) dram = mv_mbus_dram_info();
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 958) if (!dram) {
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 959) pr_err("missing DRAM information\n");
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 960) return -ENODEV;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 961) }
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 962)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 963) /* Try to find matching DRAM window for phyaddr */
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 964) for (i = 0; i < dram->num_cs; i++) {
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 965) const struct mbus_dram_window *cs = dram->cs + i;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 966)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 967) if (cs->base <= phyaddr &&
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 968) phyaddr <= (cs->base + cs->size - 1)) {
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 969) *target = dram->mbus_dram_target_id;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 970) *attr = cs->mbus_attr;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 971) return 0;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 972) }
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 973) }
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 974)
77644ad86abd2 (Arnd Bergmann 2016-03-15 11:03:39 +0100 975) pr_err("invalid dram address %pa\n", &phyaddr);
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 976) return -EINVAL;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 977) }
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 978) EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 979)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 980) int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 981) u8 *attr)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 982) {
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 983) int win;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 984)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 985) for (win = 0; win < mbus_state.soc->num_wins; win++) {
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 986) u64 wbase;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 987) int enabled;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 988)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 989) mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 990) size, target, attr, NULL);
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 991)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 992) if (!enabled)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 993) continue;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 994)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 995) if (wbase <= phyaddr && phyaddr <= wbase + *size)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 996) return win;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 997) }
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 998)
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 999) return -EINVAL;
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 1000) }
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 1001) EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
f2900acea8018 (Marcin Wojtas 2016-03-14 09:39:02 +0100 1002)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1003) static __init int mvebu_mbus_debugfs_init(void)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1004) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1005) struct mvebu_mbus_state *s = &mbus_state;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1006)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1007) /*
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1008) * If no base has been initialized, doesn't make sense to
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1009) * register the debugfs entries. We may be on a multiplatform
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1010) * kernel that isn't running a Marvell EBU SoC.
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1011) */
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1012) if (!s->mbuswins_base)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1013) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1014)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1015) s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1016) if (s->debugfs_root) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1017) s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1018) s->debugfs_root, NULL,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1019) &mvebu_sdram_debug_fops);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1020) s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1021) s->debugfs_root, NULL,
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1022) &mvebu_devs_debug_fops);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1023) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1024)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1025) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1026) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1027) fs_initcall(mvebu_mbus_debugfs_init);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1028)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1029) static int mvebu_mbus_suspend(void)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1030) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1031) struct mvebu_mbus_state *s = &mbus_state;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1032) int win;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1033)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1034) if (!s->mbusbridge_base)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1035) return -ENODEV;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1036)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1037) for (win = 0; win < s->soc->num_wins; win++) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1038) void __iomem *addr = s->mbuswins_base +
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1039) s->soc->win_cfg_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1040) void __iomem *addr_rmp;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1041)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1042) s->wins[win].base = readl(addr + WIN_BASE_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1043) s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1044)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1045) if (!mvebu_mbus_window_is_remappable(s, win))
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1046) continue;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1047)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1048) addr_rmp = s->mbuswins_base +
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1049) s->soc->win_remap_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1050)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1051) s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1052) s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1053) }
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1054)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1055) s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1056) MBUS_BRIDGE_CTRL_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1057) s->mbus_bridge_base = readl(s->mbusbridge_base +
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1058) MBUS_BRIDGE_BASE_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1059)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1060) return 0;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1061) }
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1062)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1063) static void mvebu_mbus_resume(void)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1064) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1065) struct mvebu_mbus_state *s = &mbus_state;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1066) int win;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1067)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1068) writel(s->mbus_bridge_ctrl,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1069) s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1070) writel(s->mbus_bridge_base,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1071) s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1072)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1073) for (win = 0; win < s->soc->num_wins; win++) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1074) void __iomem *addr = s->mbuswins_base +
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1075) s->soc->win_cfg_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1076) void __iomem *addr_rmp;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1077)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1078) writel(s->wins[win].base, addr + WIN_BASE_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1079) writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1080)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1081) if (!mvebu_mbus_window_is_remappable(s, win))
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1082) continue;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1083)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1084) addr_rmp = s->mbuswins_base +
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1085) s->soc->win_remap_offset(win);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1086)
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1087) writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
7fdf3d8a0316c (Michal Mazur 2014-12-30 13:43:43 +0100 1088) writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1089) }
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1090) }
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1091)
ac29abf38176e (Ben Dooks 2016-06-21 16:16:19 +0100 1092) static struct syscore_ops mvebu_mbus_syscore_ops = {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1093) .suspend = mvebu_mbus_suspend,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1094) .resume = mvebu_mbus_resume,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1095) };
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1096)
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1097) static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1098) phys_addr_t mbuswins_phys_base,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1099) size_t mbuswins_size,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1100) phys_addr_t sdramwins_phys_base,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1101) size_t sdramwins_size,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1102) phys_addr_t mbusbridge_phys_base,
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1103) size_t mbusbridge_size,
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1104) bool is_coherent)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1105) {
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1106) int win;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1107)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1108) mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1109) if (!mbus->mbuswins_base)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1110) return -ENOMEM;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1111)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1112) mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1113) if (!mbus->sdramwins_base) {
2241ed9205ed9 (Chris Packham 2020-11-12 16:21:49 +1300 1114) iounmap(mbus->mbuswins_base);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1115) return -ENOMEM;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1116) }
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1117)
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 1118) mbus->sdramwins_phys_base = sdramwins_phys_base;
4749c02b8da6d (Thomas Petazzoni 2014-11-21 17:00:04 +0100 1119)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1120) if (mbusbridge_phys_base) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1121) mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1122) mbusbridge_size);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1123) if (!mbus->mbusbridge_base) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1124) iounmap(mbus->sdramwins_base);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1125) iounmap(mbus->mbuswins_base);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1126) return -ENOMEM;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1127) }
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1128) } else
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1129) mbus->mbusbridge_base = NULL;
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1130)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1131) for (win = 0; win < mbus->soc->num_wins; win++)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1132) mvebu_mbus_disable_window(mbus, win);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1133)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1134) mbus->soc->setup_cpu_target(mbus);
bfa1ce5f38938 (Thomas Petazzoni 2015-05-28 11:40:54 +0200 1135) mvebu_mbus_setup_cpu_target_nooverlap(mbus);
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1136)
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1137) if (is_coherent)
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1138) writel(UNIT_SYNC_BARRIER_ALL,
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1139) mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1140)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1141) register_syscore_ops(&mvebu_mbus_syscore_ops);
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1142)
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1143) return 0;
fddddb52a6c4e (Thomas Petazzoni 2013-03-21 17:59:14 +0100 1144) }
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1145)
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1146) int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1147) size_t mbuswins_size,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1148) phys_addr_t sdramwins_phys_base,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1149) size_t sdramwins_size)
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1150) {
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1151) const struct of_device_id *of_id;
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1152)
7663cfd3f49f9 (Dan Carpenter 2013-11-13 10:50:24 +0300 1153) for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1154) if (!strcmp(of_id->compatible, soc))
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1155) break;
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1156)
7663cfd3f49f9 (Dan Carpenter 2013-11-13 10:50:24 +0300 1157) if (!of_id->compatible[0]) {
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1158) pr_err("could not find a matching SoC family\n");
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1159) return -ENODEV;
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1160) }
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1161)
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1162) mbus_state.soc = of_id->data;
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1163)
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1164) return mvebu_mbus_common_init(&mbus_state,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1165) mbuswins_phys_base,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1166) mbuswins_size,
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1167) sdramwins_phys_base,
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1168) sdramwins_size, 0, 0, false);
6bd6b3cb82d55 (Ezequiel Garcia 2013-07-26 10:17:44 -0300 1169) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1170)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1171) #ifdef CONFIG_OF
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1172) /*
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1173) * The window IDs in the ranges DT property have the following format:
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1174) * - bits 28 to 31: MBus custom field
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1175) * - bits 24 to 27: window target ID
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1176) * - bits 16 to 23: window attribute ID
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1177) * - bits 0 to 15: unused
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1178) */
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1179) #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1180) #define TARGET(id) (((id) & 0x0F000000) >> 24)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1181) #define ATTR(id) (((id) & 0x00FF0000) >> 16)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1182)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1183) static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1184) u32 base, u32 size,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1185) u8 target, u8 attr)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1186) {
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1187) if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 1188) pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 1189) target, attr);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1190) return -EBUSY;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1191) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1192)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1193) if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1194) target, attr)) {
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 1195) pr_err("cannot add window '%04x:%04x', too many windows\n",
ed843a7d62b99 (Thomas Petazzoni 2013-07-26 10:17:51 -0300 1196) target, attr);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1197) return -ENOMEM;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1198) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1199) return 0;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1200) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1201)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1202) static int __init
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1203) mbus_parse_ranges(struct device_node *node,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1204) int *addr_cells, int *c_addr_cells, int *c_size_cells,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1205) int *cell_count, const __be32 **ranges_start,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1206) const __be32 **ranges_end)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1207) {
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1208) const __be32 *prop;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1209) int ranges_len, tuple_len;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1210)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1211) /* Allow a node with no 'ranges' property */
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1212) *ranges_start = of_get_property(node, "ranges", &ranges_len);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1213) if (*ranges_start == NULL) {
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1214) *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1215) *ranges_start = *ranges_end = NULL;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1216) return 0;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1217) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1218) *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1219)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1220) *addr_cells = of_n_addr_cells(node);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1221)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1222) prop = of_get_property(node, "#address-cells", NULL);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1223) *c_addr_cells = be32_to_cpup(prop);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1224)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1225) prop = of_get_property(node, "#size-cells", NULL);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1226) *c_size_cells = be32_to_cpup(prop);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1227)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1228) *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1229) tuple_len = (*cell_count) * sizeof(__be32);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1230)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1231) if (ranges_len % tuple_len) {
c655f7ea4d881 (Rob Herring 2018-08-27 19:51:50 -0500 1232) pr_warn("malformed ranges entry '%pOFn'\n", node);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1233) return -EINVAL;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1234) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1235) return 0;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1236) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1237)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1238) static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1239) struct device_node *np)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1240) {
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1241) int addr_cells, c_addr_cells, c_size_cells;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1242) int i, ret, cell_count;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1243) const __be32 *r, *ranges_start, *ranges_end;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1244)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1245) ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1246) &c_size_cells, &cell_count,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1247) &ranges_start, &ranges_end);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1248) if (ret < 0)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1249) return ret;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1250)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1251) for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1252) u32 windowid, base, size;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1253) u8 target, attr;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1254)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1255) /*
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1256) * An entry with a non-zero custom field do not
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1257) * correspond to a static window, so skip it.
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1258) */
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1259) windowid = of_read_number(r, 1);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1260) if (CUSTOM(windowid))
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1261) continue;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1262)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1263) target = TARGET(windowid);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1264) attr = ATTR(windowid);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1265)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1266) base = of_read_number(r + c_addr_cells, addr_cells);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1267) size = of_read_number(r + c_addr_cells + addr_cells,
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1268) c_size_cells);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1269) ret = mbus_dt_setup_win(mbus, base, size, target, attr);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1270) if (ret < 0)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1271) return ret;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1272) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1273) return 0;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1274) }
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1275)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1276) static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1277) struct resource *mem,
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1278) struct resource *io)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1279) {
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1280) u32 reg[2];
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1281) int ret;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1282)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1283) /*
8553bcad3eca6 (Jason Gunthorpe 2013-09-17 14:11:04 -0600 1284) * These are optional, so we make sure that resource_size(x) will
8553bcad3eca6 (Jason Gunthorpe 2013-09-17 14:11:04 -0600 1285) * return 0.
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1286) */
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1287) memset(mem, 0, sizeof(struct resource));
8553bcad3eca6 (Jason Gunthorpe 2013-09-17 14:11:04 -0600 1288) mem->end = -1;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1289) memset(io, 0, sizeof(struct resource));
8553bcad3eca6 (Jason Gunthorpe 2013-09-17 14:11:04 -0600 1290) io->end = -1;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1291)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1292) ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1293) if (!ret) {
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1294) mem->start = reg[0];
a723e7523c140 (Jason Gunthorpe 2014-02-12 15:57:07 -0700 1295) mem->end = mem->start + reg[1] - 1;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1296) mem->flags = IORESOURCE_MEM;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1297) }
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1298)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1299) ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1300) if (!ret) {
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1301) io->start = reg[0];
a723e7523c140 (Jason Gunthorpe 2014-02-12 15:57:07 -0700 1302) io->end = io->start + reg[1] - 1;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1303) io->flags = IORESOURCE_IO;
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1304) }
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1305) }
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1306)
5686a1e5aa436 (Thomas Petazzoni 2014-04-14 15:47:01 +0200 1307) int __init mvebu_mbus_dt_init(bool is_coherent)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1308) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1309) struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1310) struct device_node *np, *controller;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1311) const struct of_device_id *of_id;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1312) const __be32 *prop;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1313) int ret;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1314)
087a4ab272780 (Josh Cartwright 2014-02-11 10:24:00 -0600 1315) np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1316) if (!np) {
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1317) pr_err("could not find a matching SoC family\n");
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1318) return -ENODEV;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1319) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1320)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1321) mbus_state.soc = of_id->data;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1322)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1323) prop = of_get_property(np, "controller", NULL);
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1324) if (!prop) {
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1325) pr_err("required 'controller' property missing\n");
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1326) return -EINVAL;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1327) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1328)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1329) controller = of_find_node_by_phandle(be32_to_cpup(prop));
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1330) if (!controller) {
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1331) pr_err("could not find an 'mbus-controller' node\n");
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1332) return -ENODEV;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1333) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1334)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1335) if (of_address_to_resource(controller, 0, &mbuswins_res)) {
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1336) pr_err("cannot get MBUS register address\n");
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1337) return -EINVAL;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1338) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1339)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1340) if (of_address_to_resource(controller, 1, &sdramwins_res)) {
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1341) pr_err("cannot get SDRAM register address\n");
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1342) return -EINVAL;
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1343) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1344)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1345) /*
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1346) * Set the resource to 0 so that it can be left unmapped by
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1347) * mvebu_mbus_common_init() if the DT doesn't carry the
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1348) * necessary information. This is needed to preserve backward
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1349) * compatibility.
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1350) */
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1351) memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1352)
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1353) if (mbus_state.soc->has_mbus_bridge) {
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1354) if (of_address_to_resource(controller, 2, &mbusbridge_res))
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1355) pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1356) }
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1357)
5686a1e5aa436 (Thomas Petazzoni 2014-04-14 15:47:01 +0200 1358) mbus_state.hw_io_coherency = is_coherent;
5686a1e5aa436 (Thomas Petazzoni 2014-04-14 15:47:01 +0200 1359)
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1360) /* Get optional pcie-{mem,io}-aperture properties */
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1361) mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1362) &mbus_state.pcie_io_aperture);
79d946837c042 (Ezequiel Garcia 2013-07-26 10:17:47 -0300 1363)
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1364) ret = mvebu_mbus_common_init(&mbus_state,
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1365) mbuswins_res.start,
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1366) resource_size(&mbuswins_res),
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1367) sdramwins_res.start,
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1368) resource_size(&sdramwins_res),
a0e89c02da974 (Thomas Petazzoni 2014-11-21 17:00:03 +0100 1369) mbusbridge_res.start,
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1370) resource_size(&mbusbridge_res),
a0b5cd4ac2d65 (Thomas Petazzoni 2015-01-16 17:11:28 +0100 1371) is_coherent);
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1372) if (ret)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1373) return ret;
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1374)
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1375) /* Setup statically declared windows in the DT */
bb24cab39c7b6 (Ezequiel Garcia 2013-07-26 10:17:46 -0300 1376) return mbus_dt_setup(&mbus_state, np);
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1377) }
6839cfa82f99f (Ezequiel Garcia 2013-07-26 10:17:45 -0300 1378) #endif
VisionFive2 Linux kernel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
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