ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 1) /*
c10d5c9e1200e drivers/bus/omap_l3_noc.h (Sricharan R 2014-04-11 13:09:36 -0500 2) * OMAP L3 Interconnect error handling driver header
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 3) *
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 4) * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 5) * Santosh Shilimkar <santosh.shilimkar@ti.com>
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 6) * sricharan <r.sricharan@ti.com>
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 7) *
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 8) * This program is free software; you can redistribute it and/or modify
c5f2aea0ef47b drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 13:15:43 -0500 9) * it under the terms of the GNU General Public License version 2 as
c5f2aea0ef47b drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 13:15:43 -0500 10) * published by the Free Software Foundation.
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 11) *
c5f2aea0ef47b drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 13:15:43 -0500 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
c5f2aea0ef47b drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 13:15:43 -0500 13) * kind, whether express or implied; without even the implied warranty
c5f2aea0ef47b drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 13:15:43 -0500 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 15) * GNU General Public License for more details.
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 16) */
c10d5c9e1200e drivers/bus/omap_l3_noc.h (Sricharan R 2014-04-11 13:09:36 -0500 17) #ifndef __OMAP_L3_NOC_H
c10d5c9e1200e drivers/bus/omap_l3_noc.h (Sricharan R 2014-04-11 13:09:36 -0500 18) #define __OMAP_L3_NOC_H
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 19)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 20) #define MAX_L3_MODULES 3
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 21) #define MAX_CLKDM_TARGETS 31
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 22)
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 23) #define CLEAR_STDERR_LOG (1 << 31)
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 24) #define CUSTOM_ERROR 0x2
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 25) #define STANDARD_ERROR 0x0
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 26) #define INBAND_ERROR 0x0
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 27) #define L3_APPLICATION_ERROR 0x0
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 28) #define L3_DEBUG_ERROR 0x1
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 29)
342fd144292a6 arch/arm/mach-omap2/omap_l3_noc.h (Todd Poynor 2011-08-24 19:11:39 +0530 30) /* L3 TARG register offsets */
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 31) #define L3_TARG_STDERRLOG_MAIN 0x48
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 32) #define L3_TARG_STDERRLOG_HDR 0x4c
c98aa7aaa24b7 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 12:24:56 -0500 33) #define L3_TARG_STDERRLOG_MSTADDR 0x50
cf52b2ecd719c drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 17:23:33 -0500 34) #define L3_TARG_STDERRLOG_INFO 0x58
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 35) #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
cf52b2ecd719c drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 17:23:33 -0500 36) #define L3_TARG_STDERRLOG_CINFO_INFO 0x64
c98aa7aaa24b7 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 12:24:56 -0500 37) #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 38) #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c
ed0e352073ff8 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-08-24 20:07:45 +0530 39) #define L3_FLAGMUX_REGERR0 0xc
3340d739f8e12 drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:31:33 -0500 40) #define L3_FLAGMUX_MASK0 0x8
3340d739f8e12 drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:31:33 -0500 41)
3340d739f8e12 drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:31:33 -0500 42) #define L3_TARGET_NOT_SUPPORTED NULL
3340d739f8e12 drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:31:33 -0500 43)
f33ddf745cbcd drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 14:37:03 -0500 44) #define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
f33ddf745cbcd drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 14:37:03 -0500 45)
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 46) static const char * const l3_transaction_type[] = {
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 47) /* 0 0 0 */ "Idle",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 48) /* 0 0 1 */ "Write",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 49) /* 0 1 0 */ "Read",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 50) /* 0 1 1 */ "ReadEx",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 51) /* 1 0 0 */ "Read Link",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 52) /* 1 0 1 */ "Write Non-Posted",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 53) /* 1 1 0 */ "Write Conditional",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 54) /* 1 1 1 */ "Write Broadcast",
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 55) };
7f9de02d603c4 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 15:47:28 -0500 56)
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 57) /**
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 58) * struct l3_masters_data - L3 Master information
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 59) * @id: ID of the L3 Master
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 60) * @name: master name
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 61) */
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 62) struct l3_masters_data {
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 63) u32 id;
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 64) char *name;
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 65) };
f0a6e654d8db2 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 10:11:59 -0500 66)
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 67) /**
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 68) * struct l3_target_data - L3 Target information
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 69) * @offset: Offset from base for L3 Target
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 70) * @name: Target name
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 71) *
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 72) * Target information is organized indexed by bit field definitions.
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 73) */
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 74) struct l3_target_data {
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 75) u32 offset;
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 76) char *name;
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 77) };
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 78)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 79) /**
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 80) * struct l3_flagmux_data - Flag Mux information
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 81) * @offset: offset from base for flagmux register
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 82) * @l3_targ: array indexed by flagmux index (bit offset) pointing to the
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 83) * target data. unsupported ones are marked with
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 84) * L3_TARGET_NOT_SUPPORTED
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 85) * @num_targ_data: number of entries in target data
2100b595b756d drivers/bus/omap_l3_noc.h (Afzal Mohammed 2014-04-25 17:38:11 -0500 86) * @mask_app_bits: ignore these from raw application irq status
2100b595b756d drivers/bus/omap_l3_noc.h (Afzal Mohammed 2014-04-25 17:38:11 -0500 87) * @mask_dbg_bits: ignore these from raw debug irq status
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 88) */
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 89) struct l3_flagmux_data {
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 90) u32 offset;
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 91) struct l3_target_data *l3_targ;
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 92) u8 num_targ_data;
2100b595b756d drivers/bus/omap_l3_noc.h (Afzal Mohammed 2014-04-25 17:38:11 -0500 93) u32 mask_app_bits;
2100b595b756d drivers/bus/omap_l3_noc.h (Afzal Mohammed 2014-04-25 17:38:11 -0500 94) u32 mask_dbg_bits;
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 95) };
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 96)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 97)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 98) /**
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 99) * struct omap_l3 - Description of data relevant for L3 bus.
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 100) * @dev: device representing the bus (populated runtime)
f33ddf745cbcd drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 14:37:03 -0500 101) * @l3_base: base addresses of modules (populated runtime if 0)
f33ddf745cbcd drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 14:37:03 -0500 102) * if set to L3_BASE_IS_SUBMODULE, then uses previous
f33ddf745cbcd drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 14:37:03 -0500 103) * module index as the base address
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 104) * @l3_flag_mux: array containing flag mux data per module
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 105) * offset from corresponding module base indexed per
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 106) * module.
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 107) * @num_modules: number of clock domains / modules.
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 108) * @l3_masters: array pointing to master data containing name and register
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 109) * offset for the master.
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 110) * @num_master: number of masters
d4d8819e20585 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 11:01:02 -0500 111) * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 112) * @debug_irq: irq number of the debug interrupt (populated runtime)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 113) * @app_irq: irq number of the application interrupt (populated runtime)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 114) */
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 115) struct omap_l3 {
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 116) struct device *dev;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 117)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 118) void __iomem *l3_base[MAX_L3_MODULES];
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 119) struct l3_flagmux_data **l3_flagmux;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 120) int num_modules;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 121)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 122) struct l3_masters_data *l3_masters;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 123) int num_masters;
d4d8819e20585 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 11:01:02 -0500 124) u32 mst_addr_mask;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 125)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 126) int debug_irq;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 127) int app_irq;
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 128) };
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 129)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 130) static struct l3_target_data omap_l3_target_data_clk1[] = {
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 131) {0x100, "DMM1",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 132) {0x200, "DMM2",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 133) {0x300, "ABE",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 134) {0x400, "L4CFG",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 135) {0x600, "CLK2PWRDISC",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 136) {0x0, "HOSTCLK1",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 137) {0x900, "L4WAKEUP",},
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 138) };
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 139)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 140) static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 141) .offset = 0x500,
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 142) .l3_targ = omap_l3_target_data_clk1,
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 143) .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 144) };
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 145)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 146)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 147) static struct l3_target_data omap_l3_target_data_clk2[] = {
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 148) {0x500, "CORTEXM3",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 149) {0x300, "DSS",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 150) {0x100, "GPMC",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 151) {0x400, "ISS",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 152) {0x700, "IVAHD",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 153) {0xD00, "AES1",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 154) {0x900, "L4PER0",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 155) {0x200, "OCMRAM",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 156) {0x100, "GPMCsERROR",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 157) {0x600, "SGX",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 158) {0x800, "SL2",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 159) {0x1600, "C2C",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 160) {0x1100, "PWRDISCCLK1",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 161) {0xF00, "SHA1",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 162) {0xE00, "AES2",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 163) {0xC00, "L4PER3",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 164) {0xA00, "L4PER1",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 165) {0xB00, "L4PER2",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 166) {0x0, "HOSTCLK2",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 167) {0x1800, "CAL",},
3ae9af7c90f81 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-11 11:38:10 -0500 168) {0x1700, "LLI",},
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 169) };
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 170)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 171) static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 172) .offset = 0x1000,
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 173) .l3_targ = omap_l3_target_data_clk2,
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 174) .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 175) };
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 176)
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 177)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 178) static struct l3_target_data omap4_l3_target_data_clk3[] = {
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 179) {0x0100, "DEBUGSS",},
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 180) };
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 181)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 182) static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 183) .offset = 0x0200,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 184) .l3_targ = omap4_l3_target_data_clk3,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 185) .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 186) };
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 187)
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 188) static struct l3_masters_data omap_l3_masters[] = {
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 189) { 0x00, "MPU"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 190) { 0x04, "CS_ADP"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 191) { 0x05, "xxx"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 192) { 0x08, "DSP"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 193) { 0x0C, "IVAHD"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 194) { 0x10, "ISS"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 195) { 0x11, "DucatiM3"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 196) { 0x12, "FaceDetect"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 197) { 0x14, "SDMA_Rd"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 198) { 0x15, "SDMA_Wr"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 199) { 0x16, "xxx"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 200) { 0x17, "xxx"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 201) { 0x18, "SGX"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 202) { 0x1C, "DSS"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 203) { 0x20, "C2C"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 204) { 0x22, "xxx"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 205) { 0x23, "xxx"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 206) { 0x24, "HSI"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 207) { 0x28, "MMC1"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 208) { 0x29, "MMC2"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 209) { 0x2A, "MMC6"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 210) { 0x2C, "UNIPRO1"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 211) { 0x30, "USBHOSTHS"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 212) { 0x31, "USBOTGHS"},
41fc619dd5584 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-09-10 05:20:27 -0500 213) { 0x32, "USBHOSTFS"}
551a9fa9b1f01 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-09-07 17:25:16 +0530 214) };
551a9fa9b1f01 arch/arm/mach-omap2/omap_l3_noc.h (sricharan 2011-09-07 17:25:16 +0530 215)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 216) static struct l3_flagmux_data *omap4_l3_flagmux[] = {
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 217) &omap_l3_flagmux_clk1,
97708c08c9955 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-14 09:57:50 -0500 218) &omap_l3_flagmux_clk2,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 219) &omap4_l3_flagmux_clk3,
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 220) };
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 221)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 222) static const struct omap_l3 omap4_l3_data = {
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 223) .l3_flagmux = omap4_l3_flagmux,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 224) .num_modules = ARRAY_SIZE(omap4_l3_flagmux),
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 225) .l3_masters = omap_l3_masters,
0659452dd2b26 drivers/bus/omap_l3_noc.h (Sricharan R 2013-11-26 07:38:23 -0600 226) .num_masters = ARRAY_SIZE(omap_l3_masters),
d4d8819e20585 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 11:01:02 -0500 227) /* The 6 MSBs of register field used to distinguish initiator */
d4d8819e20585 drivers/bus/omap_l3_noc.h (Nishanth Menon 2014-04-16 11:01:02 -0500 228) .mst_addr_mask = 0xFC,
2722e56de6039 arch/arm/mach-omap2/omap_l3_noc.h (Santosh Shilimkar 2011-03-07 20:53:10 +0530 229) };
c10d5c9e1200e drivers/bus/omap_l3_noc.h (Sricharan R 2014-04-11 13:09:36 -0500 230)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 231) /* OMAP5 data */
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 232) static struct l3_target_data omap5_l3_target_data_clk3[] = {
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 233) {0x0100, "L3INSTR",},
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 234) {0x0300, "DEBUGSS",},
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 235) {0x0, "HOSTCLK3",},
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 236) };
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 237)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 238) static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 239) .offset = 0x0200,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 240) .l3_targ = omap5_l3_target_data_clk3,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 241) .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 242) };
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 243)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 244) static struct l3_flagmux_data *omap5_l3_flagmux[] = {
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 245) &omap_l3_flagmux_clk1,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 246) &omap_l3_flagmux_clk2,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 247) &omap5_l3_flagmux_clk3,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 248) };
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 249)
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 250) static const struct omap_l3 omap5_l3_data = {
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 251) .l3_flagmux = omap5_l3_flagmux,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 252) .num_modules = ARRAY_SIZE(omap5_l3_flagmux),
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 253) .l3_masters = omap_l3_masters,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 254) .num_masters = ARRAY_SIZE(omap_l3_masters),
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 255) /* The 6 MSBs of register field used to distinguish initiator */
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 256) .mst_addr_mask = 0x7E0,
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 257) };
e7309c2673a38 drivers/bus/omap_l3_noc.h (Suman Anna 2015-04-24 12:54:20 -0500 258)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 259) /* DRA7 data */
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 260) static struct l3_target_data dra_l3_target_data_clk1[] = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 261) {0x2a00, "AES1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 262) {0x0200, "DMM_P1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 263) {0x0600, "DSP2_SDMA",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 264) {0x0b00, "EVE2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 265) {0x1300, "DMM_P2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 266) {0x2c00, "AES2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 267) {0x0300, "DSP1_SDMA",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 268) {0x0a00, "EVE1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 269) {0x0c00, "EVE3",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 270) {0x0d00, "EVE4",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 271) {0x2900, "DSS",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 272) {0x0100, "GPMC",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 273) {0x3700, "PCIE1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 274) {0x1600, "IVA_CONFIG",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 275) {0x1800, "IVA_SL2IF",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 276) {0x0500, "L4_CFG",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 277) {0x1d00, "L4_WKUP",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 278) {0x3800, "PCIE2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 279) {0x3300, "SHA2_1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 280) {0x1200, "GPU",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 281) {0x1000, "IPU1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 282) {0x1100, "IPU2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 283) {0x2000, "TPCC_EDMA",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 284) {0x2e00, "TPTC1_EDMA",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 285) {0x2b00, "TPTC2_EDMA",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 286) {0x0700, "VCP1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 287) {0x2500, "L4_PER2_P3",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 288) {0x0e00, "L4_PER3_P3",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 289) {0x2200, "MMU1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 290) {0x1400, "PRUSS1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 291) {0x1500, "PRUSS2"},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 292) {0x0800, "VCP1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 293) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 294)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 295) static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 296) .offset = 0x803500,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 297) .l3_targ = dra_l3_target_data_clk1,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 298) .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1),
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 299) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 300)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 301) static struct l3_target_data dra_l3_target_data_clk2[] = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 302) {0x0, "HOST CLK1",},
4adf82c35572c drivers/bus/omap_l3_noc.h (Illia Smyrnov 2015-04-16 17:42:30 -0500 303) {0x800000, "HOST CLK2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 304) {0xdead, L3_TARGET_NOT_SUPPORTED,},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 305) {0x3400, "SHA2_2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 306) {0x0900, "BB2D",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 307) {0xdead, L3_TARGET_NOT_SUPPORTED,},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 308) {0x2100, "L4_PER1_P3",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 309) {0x1c00, "L4_PER1_P1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 310) {0x1f00, "L4_PER1_P2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 311) {0x2300, "L4_PER2_P1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 312) {0x2400, "L4_PER2_P2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 313) {0x2600, "L4_PER3_P1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 314) {0x2700, "L4_PER3_P2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 315) {0x2f00, "MCASP1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 316) {0x3000, "MCASP2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 317) {0x3100, "MCASP3",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 318) {0x2800, "MMU2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 319) {0x0f00, "OCMC_RAM1",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 320) {0x1700, "OCMC_RAM2",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 321) {0x1900, "OCMC_RAM3",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 322) {0x1e00, "OCMC_ROM",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 323) {0x3900, "QSPI",},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 324) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 325)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 326) static struct l3_flagmux_data dra_l3_flagmux_clk2 = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 327) .offset = 0x803600,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 328) .l3_targ = dra_l3_target_data_clk2,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 329) .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2),
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 330) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 331)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 332) static struct l3_target_data dra_l3_target_data_clk3[] = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 333) {0x0100, "L3_INSTR"},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 334) {0x0300, "DEBUGSS_CT_TBR"},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 335) {0x0, "HOST CLK3"},
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 336) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 337)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 338) static struct l3_flagmux_data dra_l3_flagmux_clk3 = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 339) .offset = 0x200,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 340) .l3_targ = dra_l3_target_data_clk3,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 341) .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3),
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 342) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 343)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 344) static struct l3_masters_data dra_l3_masters[] = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 345) { 0x0, "MPU" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 346) { 0x4, "CS_DAP" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 347) { 0x5, "IEEE1500_2_OCP" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 348) { 0x8, "DSP1_MDMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 349) { 0x9, "DSP1_CFG" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 350) { 0xA, "DSP1_DMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 351) { 0xB, "DSP2_MDMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 352) { 0xC, "DSP2_CFG" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 353) { 0xD, "DSP2_DMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 354) { 0xE, "IVA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 355) { 0x10, "EVE1_P1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 356) { 0x11, "EVE2_P1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 357) { 0x12, "EVE3_P1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 358) { 0x13, "EVE4_P1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 359) { 0x14, "PRUSS1 PRU1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 360) { 0x15, "PRUSS1 PRU2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 361) { 0x16, "PRUSS2 PRU1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 362) { 0x17, "PRUSS2 PRU2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 363) { 0x18, "IPU1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 364) { 0x19, "IPU2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 365) { 0x1A, "SDMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 366) { 0x1B, "CDMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 367) { 0x1C, "TC1_EDMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 368) { 0x1D, "TC2_EDMA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 369) { 0x20, "DSS" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 370) { 0x21, "MMU1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 371) { 0x22, "PCIE1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 372) { 0x23, "MMU2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 373) { 0x24, "VIP1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 374) { 0x25, "VIP2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 375) { 0x26, "VIP3" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 376) { 0x27, "VPE" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 377) { 0x28, "GPU_P1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 378) { 0x29, "BB2D" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 379) { 0x29, "GPU_P2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 380) { 0x2B, "GMAC_SW" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 381) { 0x2C, "USB3" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 382) { 0x2D, "USB2_SS" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 383) { 0x2E, "USB2_ULPI_SS1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 384) { 0x2F, "USB2_ULPI_SS2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 385) { 0x30, "CSI2_1" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 386) { 0x31, "CSI2_2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 387) { 0x33, "SATA" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 388) { 0x34, "EVE1_P2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 389) { 0x35, "EVE2_P2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 390) { 0x36, "EVE3_P2" },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 391) { 0x37, "EVE4_P2" }
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 392) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 393)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 394) static struct l3_flagmux_data *dra_l3_flagmux[] = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 395) &dra_l3_flagmux_clk1,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 396) &dra_l3_flagmux_clk2,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 397) &dra_l3_flagmux_clk3,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 398) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 399)
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 400) static const struct omap_l3 dra_l3_data = {
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 401) .l3_base = { [1] = L3_BASE_IS_SUBMODULE },
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 402) .l3_flagmux = dra_l3_flagmux,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 403) .num_modules = ARRAY_SIZE(dra_l3_flagmux),
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 404) .l3_masters = dra_l3_masters,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 405) .num_masters = ARRAY_SIZE(dra_l3_masters),
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 406) /* The 6 MSBs of register field used to distinguish initiator */
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 407) .mst_addr_mask = 0xFC,
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 408) };
53a848be0a65c drivers/bus/omap_l3_noc.h (Rajendra Nayak 2014-04-10 11:33:13 -0500 409)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 410) /* AM4372 data */
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 411) static struct l3_target_data am4372_l3_target_data_200f[] = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 412) {0xf00, "EMIF",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 413) {0x1200, "DES",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 414) {0x400, "OCMCRAM",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 415) {0x700, "TPTC0",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 416) {0x800, "TPTC1",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 417) {0x900, "TPTC2"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 418) {0xb00, "TPCC",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 419) {0xd00, "DEBUGSS",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 420) {0xdead, L3_TARGET_NOT_SUPPORTED,},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 421) {0x200, "SHA",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 422) {0xc00, "SGX530",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 423) {0x500, "AES0",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 424) {0xa00, "L4_FAST",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 425) {0x300, "MPUSS_L2_RAM",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 426) {0x100, "ICSS",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 427) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 428)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 429) static struct l3_flagmux_data am4372_l3_flagmux_200f = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 430) .offset = 0x1000,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 431) .l3_targ = am4372_l3_target_data_200f,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 432) .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f),
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 433) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 434)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 435) static struct l3_target_data am4372_l3_target_data_100s[] = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 436) {0x100, "L4_PER_0",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 437) {0x200, "L4_PER_1",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 438) {0x300, "L4_PER_2",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 439) {0x400, "L4_PER_3",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 440) {0x800, "McASP0",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 441) {0x900, "McASP1",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 442) {0xC00, "MMCHS2",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 443) {0x700, "GPMC",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 444) {0xD00, "L4_FW",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 445) {0xdead, L3_TARGET_NOT_SUPPORTED,},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 446) {0x500, "ADCTSC",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 447) {0xE00, "L4_WKUP",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 448) {0xA00, "MAG_CARD",},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 449) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 450)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 451) static struct l3_flagmux_data am4372_l3_flagmux_100s = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 452) .offset = 0x600,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 453) .l3_targ = am4372_l3_target_data_100s,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 454) .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s),
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 455) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 456)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 457) static struct l3_masters_data am4372_l3_masters[] = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 458) { 0x0, "M1 (128-bit)"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 459) { 0x1, "M2 (64-bit)"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 460) { 0x4, "DAP"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 461) { 0x5, "P1500"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 462) { 0xC, "ICSS0"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 463) { 0xD, "ICSS1"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 464) { 0x14, "Wakeup Processor"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 465) { 0x18, "TPTC0 Read"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 466) { 0x19, "TPTC0 Write"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 467) { 0x1A, "TPTC1 Read"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 468) { 0x1B, "TPTC1 Write"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 469) { 0x1C, "TPTC2 Read"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 470) { 0x1D, "TPTC2 Write"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 471) { 0x20, "SGX530"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 472) { 0x21, "OCP WP Traffic Probe"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 473) { 0x22, "OCP WP DMA Profiling"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 474) { 0x23, "OCP WP Event Trace"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 475) { 0x25, "DSS"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 476) { 0x28, "Crypto DMA RD"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 477) { 0x29, "Crypto DMA WR"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 478) { 0x2C, "VPFE0"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 479) { 0x2D, "VPFE1"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 480) { 0x30, "GEMAC"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 481) { 0x34, "USB0 RD"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 482) { 0x35, "USB0 WR"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 483) { 0x36, "USB1 RD"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 484) { 0x37, "USB1 WR"},
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 485) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 486)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 487) static struct l3_flagmux_data *am4372_l3_flagmux[] = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 488) &am4372_l3_flagmux_200f,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 489) &am4372_l3_flagmux_100s,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 490) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 491)
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 492) static const struct omap_l3 am4372_l3_data = {
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 493) .l3_flagmux = am4372_l3_flagmux,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 494) .num_modules = ARRAY_SIZE(am4372_l3_flagmux),
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 495) .l3_masters = am4372_l3_masters,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 496) .num_masters = ARRAY_SIZE(am4372_l3_masters),
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 497) /* All 6 bits of register field used to distinguish initiator */
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 498) .mst_addr_mask = 0x3F,
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 499) };
27b7d5f3cc49f drivers/bus/omap_l3_noc.h (Afzal Mohammed 2013-12-02 17:48:57 +0530 500)
c10d5c9e1200e drivers/bus/omap_l3_noc.h (Sricharan R 2014-04-11 13:09:36 -0500 501) #endif /* __OMAP_L3_NOC_H */
VisionFive2 Linux kernel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
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