d2912cb15bdda (Thomas Gleixner 2019-06-04 10:11:33 +0200 1) /* SPDX-License-Identifier: GPL-2.0-only */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 2) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 3) * omap iommu: main structures
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 4) *
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 5) * Copyright (C) 2008-2009 Nokia Corporation
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 6) *
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 7) * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 8) */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 9)
533b40cccd2fb (Suman Anna 2014-10-22 17:22:22 -0500 10) #ifndef _OMAP_IOMMU_H
533b40cccd2fb (Suman Anna 2014-10-22 17:22:22 -0500 11) #define _OMAP_IOMMU_H
533b40cccd2fb (Suman Anna 2014-10-22 17:22:22 -0500 12)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 13) #include <linux/bitops.h>
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 14) #include <linux/iommu.h>
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 15)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 16) #define for_each_iotlb_cr(obj, n, __i, cr) \
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 17) for (__i = 0; \
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 18) (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 19) __i++)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 20)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 21) struct iotlb_entry {
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 22) u32 da;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 23) u32 pa;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 24) u32 pgsz, prsvd, valid;
dc308f9f92b08 (Suman Anna 2015-07-20 17:33:27 -0500 25) u32 endian, elsz, mixed;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 26) };
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 27)
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 28) /**
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 29) * struct omap_iommu_device - omap iommu device data
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 30) * @pgtable: page table used by an omap iommu attached to a domain
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 31) * @iommu_dev: pointer to store an omap iommu instance attached to a domain
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 32) */
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 33) struct omap_iommu_device {
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 34) u32 *pgtable;
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 35) struct omap_iommu *iommu_dev;
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 36) };
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 37)
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 38) /**
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 39) * struct omap_iommu_domain - omap iommu domain
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 40) * @num_iommus: number of iommus in this domain
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 41) * @iommus: omap iommu device data for all iommus in this domain
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 42) * @dev: Device using this domain.
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 43) * @lock: domain lock, should be taken when attaching/detaching
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 44) * @domain: generic domain handle used by iommu core code
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 45) */
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 46) struct omap_iommu_domain {
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 47) u32 num_iommus;
9d5018deec866 (Suman Anna 2017-09-05 17:56:18 -0500 48) struct omap_iommu_device *iommus;
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 49) struct device *dev;
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 50) spinlock_t lock;
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 51) struct iommu_domain domain;
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 52) };
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 53)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 54) struct omap_iommu {
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 55) const char *name;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 56) void __iomem *regbase;
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 57) struct regmap *syscfg;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 58) struct device *dev;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 59) struct iommu_domain *domain;
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 60) struct dentry *debug_dir;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 61)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 62) spinlock_t iommu_lock; /* global for this whole object */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 63)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 64) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 65) * We don't change iopgd for a situation like pgd for a task,
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 66) * but share it globally for each iommu.
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 67) */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 68) u32 *iopgd;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 69) spinlock_t page_table_lock; /* protect iopgd */
bfee0cf0ee1da (Josue Albarran 2017-07-28 15:49:14 -0500 70) dma_addr_t pd_dma;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 71)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 72) int nr_tlb_entries;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 73)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 74) void *ctx; /* iommu context: registres saved area */
b148d5fb2ef7b (Suman Anna 2014-02-28 14:42:37 -0600 75)
c3b44a063d3b4 (Suman Anna 2019-08-07 11:26:48 +0300 76) struct cr_regs *cr_ctx;
c3b44a063d3b4 (Suman Anna 2019-08-07 11:26:48 +0300 77) u32 num_cr_ctx;
c3b44a063d3b4 (Suman Anna 2019-08-07 11:26:48 +0300 78)
b148d5fb2ef7b (Suman Anna 2014-02-28 14:42:37 -0600 79) int has_bus_err_back;
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 80) u32 id;
01611fe8478bf (Joerg Roedel 2017-04-12 00:21:30 -0500 81)
01611fe8478bf (Joerg Roedel 2017-04-12 00:21:30 -0500 82) struct iommu_device iommu;
28ae1e3e14f32 (Joerg Roedel 2017-04-12 00:21:31 -0500 83) struct iommu_group *group;
3846a3b9511c5 (Suman Anna 2019-08-07 11:26:45 +0300 84)
3846a3b9511c5 (Suman Anna 2019-08-07 11:26:45 +0300 85) u8 pwrst;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 86) };
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 87)
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 88) /**
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 89) * struct omap_iommu_arch_data - omap iommu private data
604629bcb5057 (Tero Kristo 2019-08-07 11:26:51 +0300 90) * @iommu_dev: handle of the OMAP iommu device
604629bcb5057 (Tero Kristo 2019-08-07 11:26:51 +0300 91) * @dev: handle of the iommu device
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 92) *
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 93) * This is an omap iommu private data object, which binds an iommu user
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 94) * to its iommu device. This object should be placed at the iommu user's
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 95) * dev_archdata so generic IOMMU API can be used without having to
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 96) * utilize omap-specific plumbing anymore.
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 97) */
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 98) struct omap_iommu_arch_data {
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 99) struct omap_iommu *iommu_dev;
604629bcb5057 (Tero Kristo 2019-08-07 11:26:51 +0300 100) struct device *dev;
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 101) };
e73b7afe4e8ca (Joerg Roedel 2017-04-12 00:21:28 -0500 102)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 103) struct cr_regs {
dc308f9f92b08 (Suman Anna 2015-07-20 17:33:27 -0500 104) u32 cam;
dc308f9f92b08 (Suman Anna 2015-07-20 17:33:27 -0500 105) u32 ram;
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 106) };
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 107)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 108) struct iotlb_lock {
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 109) short base;
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 110) short vict;
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 111) };
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 112)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 113) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 114) * MMU Register offsets
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 115) */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 116) #define MMU_REVISION 0x00
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 117) #define MMU_IRQSTATUS 0x18
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 118) #define MMU_IRQENABLE 0x1c
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 119) #define MMU_WALKING_ST 0x40
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 120) #define MMU_CNTL 0x44
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 121) #define MMU_FAULT_AD 0x48
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 122) #define MMU_TTB 0x4c
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 123) #define MMU_LOCK 0x50
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 124) #define MMU_LD_TLB 0x54
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 125) #define MMU_CAM 0x58
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 126) #define MMU_RAM 0x5c
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 127) #define MMU_GFLUSH 0x60
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 128) #define MMU_FLUSH_ENTRY 0x64
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 129) #define MMU_READ_CAM 0x68
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 130) #define MMU_READ_RAM 0x6c
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 131) #define MMU_EMU_FAULT_AD 0x70
b148d5fb2ef7b (Suman Anna 2014-02-28 14:42:37 -0600 132) #define MMU_GP_REG 0x88
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 133)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 134) #define MMU_REG_SIZE 256
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 135)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 136) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 137) * MMU Register bit definitions
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 138) */
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 139) /* IRQSTATUS & IRQENABLE */
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 140) #define MMU_IRQ_MULTIHITFAULT BIT(4)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 141) #define MMU_IRQ_TABLEWALKFAULT BIT(3)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 142) #define MMU_IRQ_EMUMISS BIT(2)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 143) #define MMU_IRQ_TRANSLATIONFAULT BIT(1)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 144) #define MMU_IRQ_TLBMISS BIT(0)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 145)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 146) #define __MMU_IRQ_FAULT \
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 147) (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 148) #define MMU_IRQ_MASK \
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 149) (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 150) #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 151) #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 152)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 153) /* MMU_CNTL */
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 154) #define MMU_CNTL_SHIFT 1
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 155) #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 156) #define MMU_CNTL_EML_TLB BIT(3)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 157) #define MMU_CNTL_TWL_EN BIT(2)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 158) #define MMU_CNTL_MMU_EN BIT(1)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 159)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 160) /* CAM */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 161) #define MMU_CAM_VATAG_SHIFT 12
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 162) #define MMU_CAM_VATAG_MASK \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 163) ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 164) #define MMU_CAM_P BIT(3)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 165) #define MMU_CAM_V BIT(2)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 166) #define MMU_CAM_PGSZ_MASK 3
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 167) #define MMU_CAM_PGSZ_1M (0 << 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 168) #define MMU_CAM_PGSZ_64K (1 << 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 169) #define MMU_CAM_PGSZ_4K (2 << 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 170) #define MMU_CAM_PGSZ_16M (3 << 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 171)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 172) /* RAM */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 173) #define MMU_RAM_PADDR_SHIFT 12
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 174) #define MMU_RAM_PADDR_MASK \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 175) ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 176)
baaa7b5d4f1e5 (Laurent Pinchart 2014-07-18 12:49:55 +0200 177) #define MMU_RAM_ENDIAN_SHIFT 9
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 178) #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
baaa7b5d4f1e5 (Laurent Pinchart 2014-07-18 12:49:55 +0200 179) #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 180) #define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 181)
baaa7b5d4f1e5 (Laurent Pinchart 2014-07-18 12:49:55 +0200 182) #define MMU_RAM_ELSZ_SHIFT 7
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 183) #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 184) #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 185) #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 186) #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 187) #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 188) #define MMU_RAM_MIXED_SHIFT 6
eb642a3f5afdb (Suman Anna 2015-07-20 17:33:31 -0500 189) #define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 190) #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 191)
b148d5fb2ef7b (Suman Anna 2014-02-28 14:42:37 -0600 192) #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
b148d5fb2ef7b (Suman Anna 2014-02-28 14:42:37 -0600 193)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 194) #define get_cam_va_mask(pgsz) \
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 195) (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 196) ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 197) ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 198) ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
bd4396f09a4a9 (Suman Anna 2014-10-22 17:22:27 -0500 199)
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 200) /*
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 201) * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 202) */
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 203) #define DSP_SYS_REVISION 0x00
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 204) #define DSP_SYS_MMU_CONFIG 0x18
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 205) #define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
3ca9299e7dc65 (Suman Anna 2015-10-02 18:02:44 -0500 206)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 207) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 208) * utilities for super page(16MB, 1MB, 64KB and 4KB)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 209) */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 210)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 211) #define iopgsz_max(bytes) \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 212) (((bytes) >= SZ_16M) ? SZ_16M : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 213) ((bytes) >= SZ_1M) ? SZ_1M : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 214) ((bytes) >= SZ_64K) ? SZ_64K : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 215) ((bytes) >= SZ_4K) ? SZ_4K : 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 216)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 217) #define bytes_to_iopgsz(bytes) \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 218) (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 219) ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 220) ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 221) ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 222)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 223) #define iopgsz_to_bytes(iopgsz) \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 224) (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 225) ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 226) ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 227) ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 228)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 229) #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 230)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 231) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 232) * global functions
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 233) */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 234)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 235) struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 236) void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 237) void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 238)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 239) #ifdef CONFIG_OMAP_IOMMU_DEBUG
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 240) void omap_iommu_debugfs_init(void);
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 241) void omap_iommu_debugfs_exit(void);
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 242)
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 243) void omap_iommu_debugfs_add(struct omap_iommu *obj);
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 244) void omap_iommu_debugfs_remove(struct omap_iommu *obj);
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 245) #else
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 246) static inline void omap_iommu_debugfs_init(void) { }
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 247) static inline void omap_iommu_debugfs_exit(void) { }
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 248)
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 249) static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 250) static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 251) #endif
61c753526dc3e (Suman Anna 2014-10-22 17:22:30 -0500 252)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 253) /*
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 254) * register accessors
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 255) */
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 256) static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 257) {
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 258) return __raw_readl(obj->regbase + offs);
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 259) }
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 260)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 261) static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 262) {
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 263) __raw_writel(val, obj->regbase + offs);
ed1c7de29f9f3 (Tony Lindgren 2012-11-02 12:24:06 -0700 264) }
533b40cccd2fb (Suman Anna 2014-10-22 17:22:22 -0500 265)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 266) static inline int iotlb_cr_valid(struct cr_regs *cr)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 267) {
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 268) if (!cr)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 269) return -EINVAL;
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 270)
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 271) return cr->cam & MMU_CAM_V;
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 272) }
69c2c196328e7 (Suman Anna 2015-07-20 17:33:25 -0500 273)
533b40cccd2fb (Suman Anna 2014-10-22 17:22:22 -0500 274) #endif /* _OMAP_IOMMU_H */
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