b24413180f560 (Greg Kroah-Hartman 2017-11-01 15:07:57 +0100 1) /* SPDX-License-Identifier: GPL-2.0 */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 2) /*
fe948dcb2c122 (Amir Levy 2016-11-09 16:20:01 +0200 3) * Thunderbolt driver - NHI registers
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 4) *
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 5) * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
15c6784c7cee3 (Mika Westerberg 2018-10-01 12:31:22 +0300 6) * Copyright (C) 2018, Intel Corporation
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 7) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 8)
fe948dcb2c122 (Amir Levy 2016-11-09 16:20:01 +0200 9) #ifndef NHI_REGS_H_
fe948dcb2c122 (Amir Levy 2016-11-09 16:20:01 +0200 10) #define NHI_REGS_H_
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 11)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 12) #include <linux/types.h>
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 13)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 14) enum ring_flags {
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 15) RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 16) RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 17) RING_FLAG_PCI_NO_SNOOP = 1 << 29,
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 18) RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 19) RING_FLAG_ENABLE = 1 << 31,
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 20) };
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 21)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 22) /**
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 23) * struct ring_desc - TX/RX ring entry
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 24) *
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 25) * For TX set length/eof/sof.
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 26) * For RX length/eof/sof are set by the NHI.
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 27) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 28) struct ring_desc {
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 29) u64 phys;
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 30) u32 length:12;
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 31) u32 eof:4;
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 32) u32 sof:4;
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 33) enum ring_desc_flags flags:12;
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 34) u32 time; /* write zero */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 35) } __packed;
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 36)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 37) /* NHI registers in bar 0 */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 38)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 39) /*
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 40) * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 41) * 00: physical pointer to an array of struct ring_desc
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 42) * 08: ring tail (set by NHI)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 43) * 10: ring head (index of first non posted descriptor)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 44) * 12: descriptor count
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 45) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 46) #define REG_TX_RING_BASE 0x00000
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 47)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 48) /*
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 49) * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 50) * 00: physical pointer to an array of struct ring_desc
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 51) * 08: ring head (index of first not posted descriptor)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 52) * 10: ring tail (set by NHI)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 53) * 12: descriptor count
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 54) * 14: max frame sizes (anything larger than 0x100 has no effect)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 55) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 56) #define REG_RX_RING_BASE 0x08000
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 57)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 58) /*
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 59) * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 60) * 00: enum_ring_flags
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 61) * 04: isoch time stamp ?? (write 0)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 62) * ..: unknown
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 63) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 64) #define REG_TX_OPTIONS_BASE 0x19800
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 65)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 66) /*
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 67) * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 68) * 00: enum ring_flags
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 69) * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 70) * the corresponding TX hop id.
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 71) * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 72) * ..: unknown
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 73) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 74) #define REG_RX_OPTIONS_BASE 0x29800
9fb1e654dcf78 (Mika Westerberg 2017-10-02 13:38:36 +0300 75) #define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
9fb1e654dcf78 (Mika Westerberg 2017-10-02 13:38:36 +0300 76) #define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 77)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 78) /*
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 79) * three bitfields: tx, rx, rx overflow
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 80) * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 81) * cleared on read. New interrupts are fired only after ALL registers have been
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 82) * read (even those containing only disabled rings).
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 83) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 84) #define REG_RING_NOTIFY_BASE 0x37800
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 85) #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 86)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 87) /*
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 88) * two bitfields: rx, tx
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 89) * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 90) * enable/disable interrupts set/clear the corresponding bits.
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 91) */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 92) #define REG_RING_INTERRUPT_BASE 0x38200
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 93) #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 94)
8c6bba10fb926 (Mika Westerberg 2017-10-02 13:38:35 +0300 95) #define REG_INT_THROTTLING_RATE 0x38c00
8c6bba10fb926 (Mika Westerberg 2017-10-02 13:38:35 +0300 96)
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 97) /* Interrupt Vector Allocation */
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 98) #define REG_INT_VEC_ALLOC_BASE 0x38c40
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 99) #define REG_INT_VEC_ALLOC_BITS 4
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 100) #define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 101) #define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 102)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 103) /* The last 11 bits contain the number of hops supported by the NHI port. */
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 104) #define REG_HOP_COUNT 0x39640
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 105)
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 106) #define REG_DMA_MISC 0x39864
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 107) #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
046bee1f9ab83 (Mika Westerberg 2017-06-06 15:24:57 +0300 108)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 109) #define REG_INMAIL_DATA 0x39900
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 110)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 111) #define REG_INMAIL_CMD 0x39904
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 112) #define REG_INMAIL_CMD_MASK GENMASK(7, 0)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 113) #define REG_INMAIL_ERROR BIT(30)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 114) #define REG_INMAIL_OP_REQUEST BIT(31)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 115)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 116) #define REG_OUTMAIL_CMD 0x3990c
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 117) #define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 118) #define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
cd446ee2e64f0 (Mika Westerberg 2017-06-06 15:25:12 +0300 119)
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 120) #define REG_FW_STS 0x39944
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 121) #define REG_FW_STS_NVM_AUTH_DONE BIT(31)
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 122) #define REG_FW_STS_CIO_RESET_REQ BIT(30)
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 123) #define REG_FW_STS_ICM_EN_CPU BIT(2)
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 124) #define REG_FW_STS_ICM_EN_INVERT BIT(1)
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 125) #define REG_FW_STS_ICM_EN BIT(0)
f67cf491175a3 (Mika Westerberg 2017-06-06 15:25:16 +0300 126)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 127) /* ICL NHI VSEC registers */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 128)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 129) /* FW ready */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 130) #define VS_CAP_9 0xc8
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 131) #define VS_CAP_9_FW_READY BIT(31)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 132) /* UUID */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 133) #define VS_CAP_10 0xcc
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 134) #define VS_CAP_11 0xd0
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 135) /* LTR */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 136) #define VS_CAP_15 0xe0
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 137) #define VS_CAP_16 0xe4
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 138) /* TBT2PCIe */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 139) #define VS_CAP_18 0xec
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 140) #define VS_CAP_18_DONE BIT(0)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 141) /* PCIe2TBT */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 142) #define VS_CAP_19 0xf0
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 143) #define VS_CAP_19_VALID BIT(0)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 144) #define VS_CAP_19_CMD_SHIFT 1
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 145) #define VS_CAP_19_CMD_MASK GENMASK(7, 1)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 146) /* Force power */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 147) #define VS_CAP_22 0xfc
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 148) #define VS_CAP_22_FORCE_POWER BIT(1)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 149) #define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 150) #define VS_CAP_22_DMA_DELAY_SHIFT 24
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 151)
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 152) /**
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 153) * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 154) * @ICL_LC_GO2SX: Ask LC to enter Sx without wake
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 155) * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 156) * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 157) */
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 158) enum icl_lc_mailbox_cmd {
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 159) ICL_LC_GO2SX = 0x02,
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 160) ICL_LC_GO2SX_NO_WAKE = 0x03,
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 161) ICL_LC_PREPARE_FOR_RESET = 0x21,
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 162) };
3cdb9446a117d (Mika Westerberg 2018-01-16 22:19:00 +0200 163)
16603153666d2 (Andreas Noever 2014-06-03 22:03:58 +0200 164) #endif
VisionFive2 Linux kernel
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