VisionFive2 Linux kernel

StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

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author: Drew Fustini <drew@pdp7.com> 2021-05-20 14:52:32 -0700 committer: GitHub <noreply@github.com> 2021-05-20 14:52:32 -0700 commit: 3f001ea92b4ab9a13c3b6208fcb324e940ec988a parent: e865a75d55e0e4256242e4405b87c394b5885a57
Commit Summary:
Merge pull request #22 from cybergaszcz/nvdla
Diffstat:
33 files changed, 29167 insertions, 0 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig
index dcecc9f6e33f..e44bc1d2655b 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -235,4 +235,6 @@ source "drivers/interconnect/Kconfig"
 source "drivers/counter/Kconfig"
 
 source "drivers/most/Kconfig"
+
+source "drivers/nvdla/Kconfig"
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 576228037718..5be02ddd5052 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -189,3 +189,4 @@ obj-$(CONFIG_GNSS)		+= gnss/
 obj-$(CONFIG_INTERCONNECT)	+= interconnect/
 obj-$(CONFIG_COUNTER)		+= counter/
 obj-$(CONFIG_MOST)		+= most/
+obj-$(CONFIG_NVDLA)		+= nvdla/
diff --git a/drivers/nvdla/Kconfig b/drivers/nvdla/Kconfig
new file mode 100644
index 000000000000..8f2495fdc285
--- /dev/null
+++ b/drivers/nvdla/Kconfig
@@ -0,0 +1,5 @@
+config NVDLA
+	bool "The NVIDIA Deep Learning Accelerator"
+	default y
+	depends on DRM
+	select DRM_GEM_CMA_HELPER
diff --git a/drivers/nvdla/Makefile b/drivers/nvdla/Makefile
new file mode 100644
index 000000000000..465087fdfe38
--- /dev/null
+++ b/drivers/nvdla/Makefile
@@ -0,0 +1,19 @@
+
+ccflags-$(CONFIG_NVDLA) += -Idrivers/nvdla
+ccflags-$(CONFIG_NVDLA) += -Idrivers/nvdla/include
+
+obj-$(CONFIG_NVDLA) += scheduler.o
+obj-$(CONFIG_NVDLA) += engine.o
+obj-$(CONFIG_NVDLA) += bdma.o
+obj-$(CONFIG_NVDLA) += conv.o
+obj-$(CONFIG_NVDLA) += sdp.o
+obj-$(CONFIG_NVDLA) += cdp.o
+obj-$(CONFIG_NVDLA) += pdp.o
+obj-$(CONFIG_NVDLA) += rubik.o
+obj-$(CONFIG_NVDLA) += cache.o
+obj-$(CONFIG_NVDLA) += common.o
+obj-$(CONFIG_NVDLA) += engine_data.o
+obj-$(CONFIG_NVDLA) += engine_isr.o
+obj-$(CONFIG_NVDLA) += engine_debug.o
+obj-$(CONFIG_NVDLA) += nvdla_core_callbacks.o
+obj-$(CONFIG_NVDLA) += nvdla_gem.o
diff --git a/drivers/nvdla/bdma.c b/drivers/nvdla/bdma.c
new file mode 100644
index 000000000000..8a517410a024
--- /dev/null
+++ b/drivers/nvdla/bdma.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_mem[] = {
+	FIELD_ENUM(BDMA_CFG_CMD_0, SRC_RAM_TYPE, MC),
+	FIELD_ENUM(BDMA_CFG_CMD_0, SRC_RAM_TYPE, CVSRAM),
+};
+
+#if STAT_ENABLE
+void
+dla_bdma_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_bdma_stat_desc *bdma_stat;
+
+	bdma_stat = &processor->stat_data_desc->bdma_stat;
+
+	end_time = dla_get_time_us();
+
+	if (group->id == (uint32_t)0) {
+		bdma_stat->read_stall = bdma_reg_read(STATUS_GRP0_READ_STALL);
+		bdma_stat->write_stall = bdma_reg_read(STATUS_GRP0_WRITE_STALL);
+	} else {
+		bdma_stat->read_stall = bdma_reg_read(STATUS_GRP1_READ_STALL);
+		bdma_stat->write_stall = bdma_reg_read(STATUS_GRP1_WRITE_STALL);
+	}
+	bdma_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_bdma_dump_stat(struct dla_processor *processor)
+{
+	struct dla_bdma_stat_desc *bdma_stat;
+
+	bdma_stat = &processor->stat_data_desc->bdma_stat;
+
+	dla_debug_bdma_stats(bdma_stat);
+}
+#endif /* STAT_ENABLE */
+
+void
+dla_bdma_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	/**
+	 * There is no producer bit for BDMA operation,
+	 * interrupt pointer decides which outstanding request
+	 * to use for this BDMA operation
+	 */
+}
+
+int
+dla_bdma_enable(struct dla_processor_group *group)
+{
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (group->surface_desc->bdma_surface.num_transfers == (uint16_t)0) {
+		group->events |= ((uint8_t)1 << DLA_EVENT_OP_COMPLETED);
+		goto exit;
+	}
+
+	if (engine->stat_enable == (uint32_t)1) {
+		bdma_reg_write(CFG_STATUS, FIELD_ENUM(BDMA_CFG_STATUS_0,
+							STALL_COUNT_EN, YES));
+		group->start_time = dla_get_time_us();
+	}
+
+	/**
+	 * Launch BDMA transfer
+	 */
+	if (group->id == 0)
+		bdma_reg_write(CFG_LAUNCH0, FIELD_ENUM(BDMA_CFG_LAUNCH0_0,
+							GRP0_LAUNCH, YES));
+	else
+		bdma_reg_write(CFG_LAUNCH1, FIELD_ENUM(BDMA_CFG_LAUNCH1_0,
+							GRP1_LAUNCH, YES));
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	return 0;
+}
+
+void
+dla_bdma_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 0;
+}
+
+/**
+ * Program BDMA slot for transfer
+ */
+static int32_t
+processor_bdma_program_slot(struct dla_bdma_surface_desc *bdma_surface,
+				struct dla_bdma_transfer_desc *transfer)
+{
+	int32_t ret = 0;
+	uint64_t source_addr = 0;
+	uint64_t destination_addr = 0;
+	uint32_t high, low, reg;
+	uint8_t  bdma_free_slots = 0;
+	uint64_t bdma_len = 0;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	/* make sure there're enough free slots */
+	if (bdma_free_slots <= 0) {
+		do {
+			reg = bdma_reg_read(STATUS);
+			reg = (reg & MASK(BDMA_STATUS_0, FREE_SLOT)) >>
+					SHIFT(BDMA_STATUS_0, FREE_SLOT);
+		} while (reg == 0);
+		bdma_free_slots = (uint8_t)reg;
+	}
+
+	dla_get_dma_address(engine->driver_context, engine->task->task_data,
+						transfer->source_address,
+						(void *)&source_addr,
+						DESTINATION_DMA);
+	dla_get_dma_address(engine->driver_context, engine->task->task_data,
+						transfer->destination_address,
+						(void *)&destination_addr,
+						DESTINATION_DMA);
+
+	ASSERT_GOTO((transfer->line_repeat <= 8192),
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((transfer->surface_repeat <= 8192),
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((transfer->line_size % 32) == 0,
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->source_line >= transfer->line_size,
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->destination_line >= transfer->line_size,
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->source_surface >=
+			(transfer->source_line * transfer->line_repeat),
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->destination_surface >=
+			(transfer->destination_line * transfer->line_repeat),
+				ret, ERR(INVALID_INPUT), exit);
+
+	/* config registers */
+	high = HIGH32BITS(source_addr);
+	low = LOW32BITS(source_addr);
+	bdma_reg_write(CFG_SRC_ADDR_LOW, low);
+	bdma_reg_write(CFG_SRC_ADDR_HIGH, high);
+	high = HIGH32BITS(destination_addr);
+	low = LOW32BITS(destination_addr);
+	bdma_reg_write(CFG_DST_ADDR_LOW, low);
+	bdma_reg_write(CFG_DST_ADDR_HIGH, high);
+	bdma_reg_write(CFG_LINE, (transfer->line_size >> 5) - 1);
+	reg = (map_mem[bdma_surface->source_type] <<
+				SHIFT(BDMA_CFG_CMD_0, SRC_RAM_TYPE)) |
+		(map_mem[bdma_surface->destination_type] <<
+				SHIFT(BDMA_CFG_CMD_0, DST_RAM_TYPE));
+	bdma_reg_write(CFG_CMD, reg);
+	bdma_reg_write(CFG_LINE_REPEAT, transfer->line_repeat - 1);
+	bdma_reg_write(CFG_SRC_LINE, transfer->source_line);
+	bdma_reg_write(CFG_DST_LINE, transfer->destination_line);
+	bdma_reg_write(CFG_SURF_REPEAT, transfer->surface_repeat - 1);
+	bdma_reg_write(CFG_SRC_SURF, transfer->source_surface);
+	bdma_reg_write(CFG_DST_SURF, transfer->destination_surface);
+	bdma_reg_write(CFG_OP, FIELD_ENUM(BDMA_CFG_OP_0, EN, ENABLE));
+
+#ifdef CONFIG_NVDLA_NEED_FLUSH
+	bdma_len = (transfer->surface_repeat) * (transfer->source_surface); //???
+	nvdla_flush_dcache((unsigned long)source_addr,bdma_len);
+	nvdla_flush_dcache((unsigned long)destination_addr,bdma_len);
+	dla_info("%s():surface_repeat:%#x,source_surface:%#x  bdmalen:%#llx\n",__func__,transfer->surface_repeat,transfer->source_surface,bdma_len);
+	dla_info("%s():dma_src_addr:%#llx,dma_dst_addr:%#llx \n",__func__,source_addr,destination_addr);
+#endif
+	
+	dla_debug("Exit: %s\n", __func__);
+
+exit:
+	RETURN(ret);
+}
+
+int
+dla_bdma_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group)
+{
+	struct dla_processor_group *next_group;
+
+	next_group = &processor->groups[!group->id];
+
+	/**
+	 * If another group is already programmed but not active then
+	 * do not program this operation as BDMA does not really
+	 * have shadow copies for groups. It will end programming
+	 * same group. Wait for another group to get enabled.
+	 */
+	if ((processor->group_status & (1 << next_group->id)) &&
+						!next_group->active)
+		return 0;
+
+	return 1;
+}
+
+void
+dla_bdma_dump_config(struct dla_processor_group *group)
+{
+	struct dla_bdma_op_desc *bdma_op;
+	struct dla_bdma_surface_desc *bdma_surface;
+
+	bdma_surface = &group->surface_desc->bdma_surface;
+	bdma_op = &group->operation_desc->bdma_op;
+
+	dla_debug_bdma_surface_desc(bdma_surface, group->roi_index);
+	dla_debug_bdma_op_desc(bdma_op, group->roi_index);
+}
+
+int
+dla_bdma_program(struct dla_processor_group *group)
+{
+	int32_t i;
+	int32_t ret = 0;
+	struct dla_bdma_surface_desc *bdma_surface;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (!engine->config_data->bdma_enable) {
+		dla_error("BDMA is not supported for this configuration\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	bdma_surface = &group->surface_desc->bdma_surface;
+
+	dla_debug("Num of transfers %u\n", bdma_surface->num_transfers);
+	if (bdma_surface->num_transfers == (uint16_t)0)
+		goto exit;
+
+	if (bdma_surface->num_transfers > NUM_MAX_BDMA_OPS) {
+		dla_error("Invalid number of transfers\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	for (i = 0; i < bdma_surface->num_transfers; i++) {
+		ret = processor_bdma_program_slot(bdma_surface,
+					&bdma_surface->transfers[i]);
+		if (ret)
+			goto exit;
+	}
+
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, BDMA_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, BDMA_DONE_MASK0));
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/cache.c b/drivers/nvdla/cache.c
new file mode 100644
index 000000000000..eb1b454ef8ec
--- /dev/null
+++ b/drivers/nvdla/cache.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_engine.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+
+#define DLA_OP_CACHE_SIZE (DLA_NUM_GROUPS * ((DLA_OP_NUM + 2) * 2))
+
+static struct dla_common_op_desc desc_cache[DLA_OP_NUM][DLA_OP_CACHE_SIZE];
+static int32_t desc_refcount[DLA_OP_NUM][DLA_OP_CACHE_SIZE];
+
+void
+dla_get_refcount(struct dla_common_op_desc *op_desc)
+{
+	int32_t i;
+	struct dla_common_op_desc *desc = NULL;
+
+	if (op_desc == NULL)
+		return;
+
+	if (op_desc->index == -1)
+		return;
+
+	desc = &desc_cache[op_desc->op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == op_desc->index &&
+				desc->roi_index == op_desc->roi_index) {
+			desc_refcount[op_desc->op_type][i]++;
+			return;
+		}
+	}
+}
+
+struct dla_common_op_desc *
+dla_get_op_desc(struct dla_task *task, int16_t index,
+			uint8_t op_type, uint8_t roi_index)
+{
+	int32_t i;
+	int32_t ret;
+	uint64_t op_base;
+	uint64_t dep_graph_addr;
+	struct dla_common_op_desc *desc = NULL;
+	struct dla_engine *engine = dla_get_engine();
+
+	if (index == -1) {
+		dla_debug("no desc get due to index==-1\n");
+		goto exit;
+	}
+
+	dep_graph_addr = (sizeof(struct dla_common_op_desc) *
+				engine->network->num_operations * roi_index);
+
+	desc = &desc_cache[op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == index && desc->roi_index == roi_index) {
+			if (desc->op_type != op_type) {
+				dla_error("op_cache[op=%u] contains incorrect "
+						"entry of op[%u]\n", op_type,
+						desc->op_type);
+				continue;
+			}
+			desc_refcount[op_type][i]++;
+			goto exit;
+		}
+	}
+
+	desc = &desc_cache[op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == -1) {
+			op_base = dep_graph_addr +
+					(sizeof(struct dla_common_op_desc) *
+					(uint64_t)index);
+			ret = dla_data_read(engine->driver_context,
+					task->task_data,
+					task->dependency_graph_addr,
+					(void *)(desc),
+					sizeof(struct dla_common_op_desc),
+					op_base);
+			if (ret) {
+				desc = NULL;
+				goto exit;
+			}
+
+			if (op_type != desc->op_type) {
+				/*
+				 * op_type of entry read from DRAM should not
+				 * mismatch with given op_type. If they
+				 * mismatches, then wrong entry is fetched, so
+				 * report this issue by throwing error.
+				 */
+				dla_error("Fetched [op_type=%u] from DRAM doesn't "
+					"match with op_type[%u]\n",
+					desc->op_type,
+					op_type);
+				desc->op_type = op_type;
+				desc->index = -1;
+				desc->roi_index = -1;
+				desc = NULL;
+				goto exit;
+			}
+
+			desc->index = index;
+			desc->roi_index = roi_index;
+
+			/**
+			 * Refcount must be 0 if we are reading it first time
+			 * from DRAM
+			 */
+			assert(desc_refcount[op_type][i] == 0);
+
+			desc_refcount[op_type][i]++;
+			goto exit;
+		}
+	}
+
+exit:
+    if (desc) {
+        nvdla_flush_dcache(dw_virt_to_phys((void *)desc), sizeof(*desc));
+    }
+	return desc;
+}
+
+static void
+dla_free_op_desc(struct dla_common_op_desc *op_desc)
+{
+	uint64_t op_base;
+	uint64_t dep_graph_addr;
+	struct dla_task *task;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s op desc index %u ROI %d\n", __func__,
+				op_desc->index, op_desc->roi_index);
+
+	task = engine->task;
+	dep_graph_addr = (sizeof(struct dla_common_op_desc) *
+				engine->network->num_operations *
+				op_desc->roi_index);
+
+	if (op_desc->index == -1)
+		goto exit;
+
+	if (op_desc == NULL)
+		goto exit;
+
+	/**
+	 * TODO: keeping the depth value hardcoded as 0 for now,
+	 * need to replace it once corresponding implementation is done.
+	 */
+	op_base = (dep_graph_addr +
+			(sizeof(struct dla_common_op_desc) *
+			(uint64_t)op_desc->index));
+
+	/**
+	 * Flush descriptor to DRAM
+	 */
+	dla_data_write(engine->driver_context,
+			task->task_data,
+			(void *)op_desc,
+			task->dependency_graph_addr,
+			sizeof(struct dla_common_op_desc),
+			op_base);
+
+	/**
+	 * Release it
+	 */
+	op_desc->index = -1;
+	op_desc->roi_index = -1;
+exit:
+	dla_debug("Exit: %s\n", __func__);
+}
+
+void
+dla_put_op_desc(struct dla_common_op_desc *op_desc)
+{
+	int32_t i;
+	struct dla_common_op_desc *desc;
+
+	if (op_desc == NULL)
+		return;
+
+	if (op_desc->index == -1)
+		return;
+
+	desc = &desc_cache[op_desc->op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == op_desc->index &&
+				desc->roi_index == op_desc->roi_index) {
+			/**
+			 * Refcount can't be 0 when we are trying to free it
+			 */
+			assert(desc_refcount[op_desc->op_type][i] > 0);
+
+			desc_refcount[op_desc->op_type][i]--;
+
+			/**
+			 * Free desc if refcount is 0
+			 */
+			if (desc_refcount[op_desc->op_type][i] == 0)
+				dla_free_op_desc(op_desc);
+
+			return;
+		}
+	}
+}
+
+void
+dla_init_op_cache(struct dla_engine *engine)
+{
+	int32_t i, j;
+	struct dla_common_op_desc *desc = &desc_cache[0][0];
+
+	dla_memset((uint8_t *)&desc_cache[0][0], 0, sizeof(desc_cache));
+	dla_memset((uint8_t *)&desc_refcount[0][0], 0, sizeof(desc_refcount));
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		for (j = 0; j < DLA_OP_CACHE_SIZE; j++) {
+			desc->index = -1;
+			desc->roi_index = -1;
+			desc->op_type = (uint8_t)i;
+			desc++;
+		}
+	}
+}
diff --git a/drivers/nvdla/cdp.c b/drivers/nvdla/cdp.c
new file mode 100644
index 000000000000..e83967698127
--- /dev/null
+++ b/drivers/nvdla/cdp.c
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_ram[] = {
+	FIELD_ENUM(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE, MC),
+	FIELD_ENUM(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE, CV),
+};
+
+static const uint8_t map_precision[] = {
+	FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, INT8),
+	FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, INT16),
+	FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, FP16),
+};
+
+static const uint8_t map_perf_dma[] = {
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, DMA_EN, DISABLE),
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, DMA_EN, ENABLE),
+};
+
+static const uint8_t map_perf_lut[] = {
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, LUT_EN, DISABLE),
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, LUT_EN, ENABLE),
+};
+
+#if STAT_ENABLE
+void
+dla_cdp_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_cdp_stat_desc *cdp_stat;
+
+	cdp_stat = &processor->stat_data_desc->cdp_stat;
+
+	end_time = dla_get_time_us();
+
+	cdp_stat->write_stall = cdp_reg_read(D_PERF_WRITE_STALL);
+	cdp_stat->lut_uflow = cdp_reg_read(D_PERF_LUT_UFLOW);
+	cdp_stat->lut_oflow = cdp_reg_read(D_PERF_LUT_OFLOW);
+	cdp_stat->lut_hybrid = cdp_reg_read(D_PERF_LUT_HYBRID);
+	cdp_stat->lut_le_hit = cdp_reg_read(D_PERF_LUT_LE_HIT);
+	cdp_stat->lut_lo_hit = cdp_reg_read(D_PERF_LUT_LO_HIT);
+	cdp_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_cdp_dump_stat(struct dla_processor *processor)
+{
+	struct dla_cdp_stat_desc *cdp_stat;
+
+	cdp_stat = &processor->stat_data_desc->cdp_stat;
+
+	dla_debug_cdp_stats(cdp_stat);
+}
+#endif /* STAT_ENABLE */
+
+static uint32_t
+map_local_size(uint8_t local_size)
+{
+	return ((local_size-1)/2)-1;
+}
+
+void
+dla_cdp_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	uint32_t reg;
+
+	/**
+	 * set producer pointer for all sub-modules
+	 */
+	reg = group_id << SHIFT(CDP_S_POINTER_0, PRODUCER);
+	cdp_reg_write(S_POINTER, reg);
+	reg = group_id << SHIFT(CDP_RDMA_S_POINTER_0, PRODUCER);
+	cdp_rdma_reg_write(S_POINTER, reg);
+}
+
+int
+dla_cdp_enable(struct dla_processor_group *group)
+{
+	uint32_t reg;
+	uint8_t perf_reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (engine->stat_enable == (uint32_t)1) {
+		perf_reg = (map_perf_dma[1] <<
+				SHIFT(CDP_D_PERF_ENABLE_0, DMA_EN)) |
+			(map_perf_lut[1] <<
+				SHIFT(CDP_D_PERF_ENABLE_0, LUT_EN));
+
+		cdp_reg_write(D_PERF_ENABLE, perf_reg);
+		group->start_time = dla_get_time_us();
+	}
+
+	/**
+	 * enable all sub-modules
+	 */
+	reg = FIELD_ENUM(CDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
+	cdp_rdma_reg_write(D_OP_ENABLE, reg);
+	reg = FIELD_ENUM(CDP_D_OP_ENABLE_0, OP_EN, ENABLE);
+	cdp_reg_write(D_OP_ENABLE, reg);
+
+	dla_debug("Exit: %s\n", __func__);
+
+	RETURN(0);
+}
+
+void
+dla_cdp_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 1;
+}
+
+static int32_t
+processor_cdp_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg, high, low;
+	uint64_t input_address = 0;
+	uint64_t output_address = 0;
+	struct dla_lut_param lut;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_cdp_op_desc *cdp_op;
+	struct dla_cdp_surface_desc *cdp_surface;
+
+	dla_debug("Enter: %s\n", __func__);
+
+	cdp_op = &group->operation_desc->cdp_op;
+	cdp_surface = &group->surface_desc->cdp_surface;
+
+	/* Argument check */
+	if (cdp_surface->src_data.type == DLA_MEM_HW) {
+		dla_error("Invalid source memory type\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+	if (cdp_surface->dst_data.type == DLA_MEM_HW) {
+		dla_error("Invalid destination memory type\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (cdp_op->in_precision != cdp_op->out_precision) {
+		dla_error("CDP does not support precision conversion\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	/* get the addresses from task descriptor */
+	ret = dla_read_input_address(&cdp_surface->src_data,
+						&input_address,
+						group->op_desc->index,
+						group->roi_index,
+						1);
+	if (ret)
+		goto exit;
+
+	dla_get_dma_cube_address(engine->driver_context,
+				engine->task->task_data,
+				cdp_surface->dst_data.address,
+				cdp_surface->dst_data.offset,
+				(void *)&output_address,
+				DESTINATION_DMA);
+	if (cdp_op->lut_index >= 0) {
+		group->lut_index = cdp_op->lut_index;
+		dla_read_lut(engine, cdp_op->lut_index, (void *)&lut);
+		dla_debug_lut_params(&lut);
+	}
+
+	/* config CDP RDMA registers */
+	reg = ((cdp_surface->src_data.width - 1)
+		<< SHIFT(CDP_RDMA_D_DATA_CUBE_WIDTH_0, WIDTH));
+	cdp_rdma_reg_write(D_DATA_CUBE_WIDTH, reg);
+
+	reg = ((cdp_surface->src_data.height - 1)
+		<< SHIFT(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, HEIGHT));
+	cdp_rdma_reg_write(D_DATA_CUBE_HEIGHT, reg);
+
+	reg = ((cdp_surface->src_data.channel - 1)
+		<< SHIFT(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, CHANNEL));
+	cdp_rdma_reg_write(D_DATA_CUBE_CHANNEL, reg);
+
+	high = HIGH32BITS(input_address);
+	low = LOW32BITS(input_address);
+	cdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
+	cdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
+
+	cdp_rdma_reg_write(D_SRC_LINE_STRIDE,
+			cdp_surface->src_data.line_stride);
+	cdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
+			cdp_surface->src_data.surf_stride);
+
+	reg = (map_ram[cdp_surface->src_data.type]
+		<< SHIFT(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE));
+	cdp_rdma_reg_write(D_SRC_DMA_CFG, reg);
+
+	reg = (map_precision[cdp_op->in_precision]
+		<< SHIFT(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA));
+	cdp_rdma_reg_write(D_DATA_FORMAT, reg);
+
+	/* config CDP */
+	if (cdp_op->lut_index >= 0)
+		update_lut(CDP_S_LUT_ACCESS_CFG_0, &lut, cdp_op->in_precision);
+
+	high = HIGH32BITS(output_address);
+	low = LOW32BITS(output_address);
+	cdp_reg_write(D_DST_BASE_ADDR_LOW, low);
+	cdp_reg_write(D_DST_BASE_ADDR_HIGH, high);
+
+	cdp_reg_write(D_DST_LINE_STRIDE, cdp_surface->dst_data.line_stride);
+	cdp_reg_write(D_DST_SURFACE_STRIDE, cdp_surface->dst_data.surf_stride);
+
+	reg = (map_ram[cdp_surface->dst_data.type]
+		<< SHIFT(CDP_D_DST_DMA_CFG_0, DST_RAM_TYPE));
+	cdp_reg_write(D_DST_DMA_CFG, reg);
+
+	reg = (map_precision[cdp_op->in_precision]
+		<< SHIFT(CDP_D_DATA_FORMAT_0, INPUT_DATA_TYPE));
+	cdp_reg_write(D_DATA_FORMAT, reg);
+
+	reg = (map_local_size(cdp_op->local_size)
+		<< SHIFT(CDP_D_LRN_CFG_0, NORMALZ_LEN));
+	cdp_reg_write(D_LRN_CFG, reg);
+
+	reg = (cdp_op->in_cvt.offset
+		<< SHIFT(CDP_D_DATIN_OFFSET_0, DATIN_OFFSET));
+	cdp_reg_write(D_DATIN_OFFSET, reg);
+
+	reg = (cdp_op->in_cvt.scale
+		<< SHIFT(CDP_D_DATIN_SCALE_0, DATIN_SCALE));
+	cdp_reg_write(D_DATIN_SCALE, reg);
+
+	reg = (cdp_op->in_cvt.truncate
+		<< SHIFT(CDP_D_DATIN_SHIFTER_0, DATIN_SHIFTER));
+	cdp_reg_write(D_DATIN_SHIFTER, reg);
+
+	reg = (cdp_op->out_cvt.offset
+		<< SHIFT(CDP_D_DATOUT_OFFSET_0, DATOUT_OFFSET));
+	cdp_reg_write(D_DATOUT_OFFSET, reg);
+
+	reg = (cdp_op->out_cvt.scale
+		<< SHIFT(CDP_D_DATOUT_SCALE_0, DATOUT_SCALE));
+	cdp_reg_write(D_DATOUT_SCALE, reg);
+
+	reg = (cdp_op->out_cvt.truncate
+		<< SHIFT(CDP_D_DATOUT_SHIFTER_0, DATOUT_SHIFTER));
+	cdp_reg_write(D_DATOUT_SHIFTER, reg);
+
+	reg = ((cdp_op->bypass_sqsum ?
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS, ENABLE) :
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS, DISABLE)) <<
+		SHIFT(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS)) |
+		((cdp_op->bypass_out_mul ?
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, MUL_BYPASS, ENABLE) :
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, MUL_BYPASS, DISABLE)) <<
+		SHIFT(CDP_D_FUNC_BYPASS_0, MUL_BYPASS));
+	cdp_reg_write(D_FUNC_BYPASS, reg);
+
+exit:
+	dla_debug("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_cdp_is_ready(struct dla_processor *processor,
+		 struct dla_processor_group *group)
+{
+	struct dla_processor_group *next_group;
+	struct dla_cdp_op_desc *cdp_op;
+
+	cdp_op = &group->operation_desc->cdp_op;
+	next_group = &processor->groups[!group->id];
+
+	/**
+	 * Single LUT is shared between two CDP groups, need to make
+	 * sure that usage does not conflict. Also, LUT write
+	 * access is locked when CDP sub-engine is active, so delay
+	 * writing LUT when another group is active.
+	 */
+
+	/**
+	 * if no LUT required for current group then it can be programmed
+	 * without further checks
+	 */
+	if (cdp_op->lut_index == -1)
+		return 1;
+
+	/**
+	 * if same LUT is used for both groups then it can be programmed
+	 * without more checks. Even if another group is active and LUT
+	 * is locked, it would have been programmed by another group.
+	 */
+	if (next_group->lut_index == cdp_op->lut_index)
+		return 1;
+
+	/**
+	 * if LUT index of another group is not -1 means some LUT is programmed,
+	 * then do not program current LUT as we already know current LUT is not
+	 * -1 and neither same as another group.
+	 */
+	if (next_group->lut_index != -1)
+		return 0;
+
+	/**
+	 * if current group needs LUT different than another group and that
+	 * group is not active then program it.
+	 */
+	if (!next_group->active)
+		return 1;
+
+	/**
+	 * if control is here it means current group is using LUT different than
+	 * another group and that group is active. Wait for another group to
+	 * become idle.
+	 */
+
+	return 0;
+}
+
+void
+dla_cdp_dump_config(struct dla_processor_group *group)
+{
+	struct dla_cdp_op_desc *cdp_op;
+	struct dla_cdp_surface_desc *cdp_surface;
+
+	cdp_surface = &group->surface_desc->cdp_surface;
+	cdp_op = &group->operation_desc->cdp_op;
+
+	dla_debug_cdp_surface_desc(cdp_surface, group->roi_index);
+	dla_debug_cdp_op_desc(cdp_op, group->roi_index);
+}
+
+int
+dla_cdp_program(struct dla_processor_group *group)
+{
+	int32_t ret;
+
+	dla_debug("Enter: %s", __func__);
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, CDP_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, CDP_DONE_MASK0));
+
+	ret = processor_cdp_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_debug("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/common.c b/drivers/nvdla/common.c
new file mode 100644
index 000000000000..c36c6ff3cc78
--- /dev/null
+++ b/drivers/nvdla/common.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+
+static const uint8_t map_lut_method[] = {
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION, EXPONENT),
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION, LINEAR)
+};
+static const uint8_t map_lut_out[] = {
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY, LE),
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY, LO)
+};
+
+static const uint16_t access_data_offset[] = {
+	CDP_S_LUT_ACCESS_DATA_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_ACCESS_DATA_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lut_cfg_offset[] = {
+	CDP_S_LUT_CFG_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_CFG_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lut_info_offset[] = {
+	CDP_S_LUT_INFO_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_INFO_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_start_offset[] = {
+	CDP_S_LUT_LE_START_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_START_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_end_offset[] = {
+	CDP_S_LUT_LE_END_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_END_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_start_offset[] = {
+	CDP_S_LUT_LO_START_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_START_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_end_offset[] = {
+	CDP_S_LUT_LO_END_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_END_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_slope_scale_offset[] = {
+	CDP_S_LUT_LE_SLOPE_SCALE_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_SLOPE_SCALE_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_slope_shift_offset[] = {
+	CDP_S_LUT_LE_SLOPE_SHIFT_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_SLOPE_SHIFT_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_slope_scale_offset[] = {
+	CDP_S_LUT_LO_SLOPE_SCALE_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_SLOPE_SCALE_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_slope_shift_offset[] = {
+	CDP_S_LUT_LO_SLOPE_SHIFT_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_SLOPE_SHIFT_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+
+void update_lut(uint32_t reg_base, struct dla_lut_param *lut,
+							uint8_t precision)
+{
+	int32_t i;
+	uint32_t reg;
+	uint32_t high, low;
+	int32_t is_sdp = reg_base == SDP_S_LUT_ACCESS_CFG_0;
+	struct dla_engine *engine = dla_get_engine();
+
+	/* program raw table */
+	reg = (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID, LE)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID)) |
+		(FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE, WRITE)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE));
+	reg_write(reg_base, reg);
+
+	for (i = 0; i < (1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1; i++) {
+		dla_reg_write(engine->driver_context,
+				reg_base + access_data_offset[is_sdp],
+				lut->linear_exp_table[i]);
+	}
+
+	/* program density table */
+	reg = (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID, LO)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID)) |
+		(FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE, WRITE)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE));
+	dla_reg_write(engine->driver_context, reg_base, reg);
+
+	for (i = 0; i < (1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1; i++) {
+		dla_reg_write(engine->driver_context,
+				reg_base + access_data_offset[is_sdp],
+				lut->linear_only_table[i]);
+	}
+
+	/* program other configurations */
+	reg = (map_lut_method[lut->method] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION)) |
+		(map_lut_out[lut->hybrid_priority] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_HYBRID_PRIORITY)) |
+		(map_lut_out[lut->underflow_priority] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY)) |
+		(map_lut_out[lut->overflow_priority] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_OFLOW_PRIORITY));
+	dla_reg_write(engine->driver_context,
+			reg_base + lut_cfg_offset[is_sdp], reg);
+
+	if (lut->method == FIELD_ENUM(CDP_S_LUT_CFG_0,
+					LUT_LE_FUNCTION, EXPONENT)) {
+		reg = ((((uint32_t)lut->linear_exp_offset.exp_offset) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LE_INDEX_OFFSET))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LE_INDEX_OFFSET)) |
+			((((uint32_t)lut->linear_only_offset.frac_bits) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT));
+	} else {
+		reg = ((((uint32_t)lut->linear_exp_offset.frac_bits) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LE_INDEX_SELECT))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LE_INDEX_SELECT)) |
+			((((uint32_t)lut->linear_only_offset.frac_bits) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT));
+	}
+	dla_reg_write(engine->driver_context,
+			reg_base + lut_info_offset[is_sdp], reg);
+	high = HIGH32BITS(lut->linear_exp_start);
+	low = LOW32BITS(lut->linear_exp_start);
+	dla_reg_write(engine->driver_context,
+			reg_base + le_start_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + le_start_offset[is_sdp] + 4, high);
+
+	high = HIGH32BITS(lut->linear_exp_end);
+	low = LOW32BITS(lut->linear_exp_end);
+	dla_reg_write(engine->driver_context,
+				reg_base + le_end_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + le_end_offset[is_sdp] + 4, high);
+
+	high = HIGH32BITS(lut->linear_only_start);
+	low = LOW32BITS(lut->linear_only_start);
+	dla_reg_write(engine->driver_context,
+				reg_base + lo_start_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_start_offset[is_sdp] + 4, high);
+
+	high = HIGH32BITS(lut->linear_only_end);
+	low = LOW32BITS(lut->linear_only_end);
+	dla_reg_write(engine->driver_context,
+				reg_base + lo_end_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_end_offset[is_sdp] + 4, high);
+
+	if (precision == PRECISION_FP16) {
+		reg = (lut->linear_exp_underflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_UFLOW_SCALE)) |
+			(lut->linear_exp_overflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + le_slope_scale_offset[is_sdp], reg);
+
+		reg = (lut->linear_only_underflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_UFLOW_SCALE)) |
+			(lut->linear_only_overflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_slope_scale_offset[is_sdp], reg);
+	} else {
+		union dla_slope *oslope;
+		union dla_slope *uslope;
+
+		uslope = &lut->linear_exp_underflow_slope;
+		oslope = &lut->linear_exp_overflow_slope;
+		reg = ((((uint32_t)uslope->data_i.scale)
+			<< SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_UFLOW_SCALE))&
+			MASK(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_UFLOW_SCALE)) |
+			((((uint32_t)oslope->data_i.scale)
+			<< SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_OFLOW_SCALE))&
+			MASK(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + le_slope_scale_offset[is_sdp], reg);
+
+		reg = ((((uint32_t)uslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_UFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_UFLOW_SHIFT)) |
+			((((uint32_t)oslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_OFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_OFLOW_SHIFT));
+		dla_reg_write(engine->driver_context,
+				reg_base + le_slope_shift_offset[is_sdp], reg);
+
+		uslope = &lut->linear_only_underflow_slope;
+		oslope = &lut->linear_only_overflow_slope;
+		reg = ((((uint32_t)uslope->data_i.scale) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_UFLOW_SCALE))&
+			MASK(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_UFLOW_SCALE)) |
+			((((uint32_t)oslope->data_i.scale) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_OFLOW_SCALE))&
+			MASK(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_slope_scale_offset[is_sdp], reg);
+		reg = ((((uint32_t)uslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_UFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_UFLOW_SHIFT)) |
+			((((uint32_t)oslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_OFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_OFLOW_SHIFT));
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_slope_shift_offset[is_sdp], reg);
+	}
+}
+
+int
+validate_data_cube(struct dla_data_cube src_data_cube,
+			struct dla_data_cube dst_data_cube,
+			uint8_t mem_type)
+{
+	int32_t ret = 0;
+
+	dla_trace("Enter: %s", __func__);
+
+	if ((src_data_cube.width > DCUBE_MAX_WIDTH) ||
+	    (src_data_cube.height > DCUBE_MAX_HEIGHT) ||
+	    (src_data_cube.channel > DCUBE_MAX_CHANNEL)) {
+		dla_error("Invalid SrcInput Cude[W: %u, H: %u, C: %u]",
+				src_data_cube.width, src_data_cube.height,
+				src_data_cube.channel);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if ((dst_data_cube.width > DCUBE_MAX_WIDTH) ||
+	    (dst_data_cube.height > DCUBE_MAX_HEIGHT) ||
+	    (dst_data_cube.channel > DCUBE_MAX_CHANNEL)) {
+		dla_error("Invalid DstInput Cude[W: %u, H: %u, C: %u]",
+				dst_data_cube.width, dst_data_cube.height,
+				dst_data_cube.channel);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (src_data_cube.type > mem_type) {
+		dla_error("Invalid src_data.mem_type: %u\n", src_data_cube.type);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (dst_data_cube.type > mem_type) {
+		dla_error("Invalid dst_data.mem_type: %u\n", dst_data_cube.type);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+validate_precision(uint8_t precision, uint8_t map_precision)
+{
+	int32_t ret = 0;
+
+	if (precision >= map_precision) {
+		dla_error("Invalid precision: %u\n", precision);
+		ret = ERR(INVALID_INPUT);
+	}
+
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/common.h b/drivers/nvdla/common.h
new file mode 100644
index 000000000000..2605cfc6e8d8
--- /dev/null
+++ b/drivers/nvdla/common.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_COMMON_H_
+#define __FIRMWARE_COMMON_H_
+
+#include <dla_interface.h>
+
+#define DCUBE_MAX_WIDTH		8192
+#define DCUBE_MAX_HEIGHT	8192
+#define DCUBE_MAX_CHANNEL	8192
+
+void update_lut(uint32_t reg_base,
+		struct dla_lut_param *lut,
+		uint8_t precision);
+int32_t validate_data_cube(struct dla_data_cube src_data_cube,
+			struct dla_data_cube dst_data_cube,
+			uint8_t mem_type);
+int32_t validate_precision(uint8_t precision,
+			uint8_t map_precision);
+
+#endif /* __FIRMWARE_COMMON_H_ */
diff --git a/drivers/nvdla/conv.c b/drivers/nvdla/conv.c
new file mode 100644
index 000000000000..be62d65d9b57
--- /dev/null
+++ b/drivers/nvdla/conv.c
@@ -0,0 +1,779 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_precision[] = {
+	FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, INT8),
+	FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, INT16),
+	FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, FP16),
+};
+
+static const uint8_t map_conv[] = {
+	FIELD_ENUM(CACC_D_MISC_CFG_0, CONV_MODE, DIRECT),
+	FIELD_ENUM(CACC_D_MISC_CFG_0, CONV_MODE, WINOGRAD),
+};
+
+static const uint8_t map_weight_fmt[] = {
+	FIELD_ENUM(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT, UNCOMPRESSED),
+	FIELD_ENUM(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT, COMPRESSED),
+};
+
+static const uint8_t map_img_fmt[][2] = {
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R8), 1},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R10), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R12), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R16), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R16_I), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R16_F), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16B16G16R16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_X16B16G16R16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16B16G16R16_F), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16Y16U16V16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_V16U16Y16A16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16Y16U16V16_F), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A8B8G8R8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A8R8G8B8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_B8G8R8A8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R8G8B8A8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_X8B8G8R8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_X8R8G8B8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_B8G8R8X8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R8G8B8X8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A2B10G10R10), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A2R10G10B10), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_B10G10R10A2), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R10G10B10A2), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A2Y10U10V10), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_V10U10Y10A2), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A8Y8U8V8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_V8U8Y8A8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y8___U8V8_N444), 1},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y8___V8U8_N444), 1},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y10___U10V10_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y10___V10U10_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y12___U12V12_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y12___V12U12_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y16___U16V16_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y16___V16U16_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			DATAIN_FORMAT, FEATURE), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			DATAIN_FORMAT, PIXEL), 1},
+};
+
+static const uint8_t map_pixel[] = {
+	FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0, PIXEL_MAPPING, PITCH_LINEAR),
+};
+
+static const uint8_t map_ram[] = {
+	FIELD_ENUM(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, MCIF),
+	FIELD_ENUM(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, CVIF),
+};
+
+static const uint8_t map_mean[] = {
+	FIELD_ENUM(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT, DISABLE),
+	FIELD_ENUM(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT, ENABLE),
+};
+
+#if STAT_ENABLE
+void
+dla_conv_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_conv_stat_desc *conv_stat;
+
+	conv_stat = &processor->stat_data_desc->conv_stat;
+
+	end_time = dla_get_time_us();
+
+	conv_stat->data_read_stall = cdma_reg_read(D_PERF_DAT_READ_STALL);
+	conv_stat->weight_read_stall = cdma_reg_read(D_PERF_WT_READ_STALL);
+	conv_stat->data_read_latency = cdma_reg_read(D_PERF_DAT_READ_LATENCY);
+	conv_stat->weight_read_latency = cdma_reg_read(D_PERF_WT_READ_LATENCY);
+	conv_stat->nan_data_num = cdma_reg_read(D_NAN_INPUT_DATA_NUM);
+	conv_stat->nan_weight_num = cdma_reg_read(D_NAN_INPUT_WEIGHT_NUM);
+	conv_stat->inf_data_num = cdma_reg_read(D_INF_INPUT_DATA_NUM);
+	conv_stat->inf_weight_num = cdma_reg_read(D_INF_INPUT_WEIGHT_NUM);
+	conv_stat->saturation_count = cacc_reg_read(D_OUT_SATURATION);
+	conv_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_conv_dump_stat(struct dla_processor *processor)
+{
+	struct dla_conv_stat_desc *conv_stat;
+
+	conv_stat = &processor->stat_data_desc->conv_stat;
+
+	dla_debug_conv_stats(conv_stat);
+}
+#endif /* STAT_ENABLE */
+
+static uint32_t
+get_in_format(uint8_t format)
+{
+	uint32_t in_format = 0;
+
+	if (format >= FORMAT_T_R8 && format < FORMAT_FEATURE) {
+		in_format = FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+						DATAIN_FORMAT, PIXEL);
+	} else if (format == FORMAT_FEATURE) {
+		in_format = FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+						DATAIN_FORMAT, FEATURE);
+	} else {
+		assert(0);
+	}
+
+	return in_format;
+}
+
+void
+dla_conv_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	uint32_t reg;
+
+	/* set producer pointer for all sub-modules */
+	reg = group_id << SHIFT(CACC_S_POINTER_0, PRODUCER);
+	cacc_reg_write(S_POINTER, reg);
+	cmac_a_reg_write(S_POINTER, reg);
+	cmac_b_reg_write(S_POINTER, reg);
+	csc_reg_write(S_POINTER, reg);
+	cdma_reg_write(S_POINTER, reg);
+}
+
+int
+dla_conv_enable(struct dla_processor_group *group)
+{
+	uint32_t reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_trace("Enter: %s", __func__);
+
+	do {
+		reg = cdma_reg_read(S_CBUF_FLUSH_STATUS);
+	} while (!(reg & MASK(CDMA_S_CBUF_FLUSH_STATUS_0, FLUSH_DONE)));
+
+	if (engine->stat_enable == (uint32_t)1) {
+		cdma_reg_write(D_PERF_ENABLE, 1);
+		group->start_time = dla_get_time_us();
+	}
+
+	/* enable all sub-modules */
+	reg = FIELD_ENUM(CACC_D_OP_ENABLE_0, OP_EN, ENABLE);
+	cacc_reg_write(D_OP_ENABLE, reg);
+	cmac_a_reg_write(D_OP_ENABLE, reg);
+	cmac_b_reg_write(D_OP_ENABLE, reg);
+	csc_reg_write(D_OP_ENABLE, reg);
+	cdma_reg_write(D_OP_ENABLE, reg);
+
+	dla_trace("Exit: %s", __func__);
+
+	RETURN(0);
+}
+
+void
+dla_conv_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 0;
+}
+
+static int32_t
+processor_conv_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg, high, low, shift, mask;
+	uint32_t stride_x, stride_y, pad_x, pad_y;
+	uint64_t weight_address = 0;
+	uint64_t wmb_address = 0;
+	uint64_t wgs_address = 0;
+	uint64_t input_address = 0;
+	uint64_t output_address = 0;
+	uint32_t atom_size = 0;
+	bool weight_compress_support = false;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_conv_op_desc *conv_op;
+	struct dla_conv_surface_desc *conv_surface;
+
+	dla_trace("Enter: %s", __func__);
+
+	weight_compress_support = engine->config_data->weight_compress_support;
+	atom_size = engine->config_data->atom_size;
+	conv_op = &group->operation_desc->conv_op;
+	conv_surface = &group->surface_desc->conv_surface;
+
+	if (conv_op->weight_format == WEIGHT_FORMAT_COMPRESSED) {
+		ASSERT_GOTO((weight_compress_support), ret, ERR(INVALID_INPUT), exit);
+		ASSERT_GOTO((conv_surface->wmb_data.address != -1),
+			ret, ERR(INVALID_INPUT), exit);
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->wmb_data.address,
+					conv_surface->wmb_data.offset,
+					(void *)&wmb_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(wmb_address, atom_size);
+		CHECK_ALIGN(conv_surface->wmb_data.size, 128);
+
+		ASSERT_GOTO((conv_surface->wgs_data.address != -1),
+			ret, ERR(INVALID_INPUT), exit);
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->wgs_data.address,
+					conv_surface->wgs_data.offset,
+					(void *)&wgs_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(wgs_address, atom_size);
+		CHECK_ALIGN(conv_surface->wgs_data.size, 4);
+	}
+
+	if (conv_surface->weight_data.address != -1) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->weight_data.address,
+					conv_surface->weight_data.offset,
+					(void *)&weight_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(weight_address, atom_size);
+		CHECK_ALIGN(conv_surface->weight_data.size, 128);
+	}
+
+	if (conv_surface->dst_data.address != -1) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->dst_data.address,
+					conv_surface->dst_data.offset,
+					(void *)&output_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(output_address, atom_size);
+		CHECK_ALIGN(conv_surface->dst_data.size, atom_size);
+		CHECK_ALIGN(conv_surface->dst_data.line_stride, atom_size);
+		CHECK_ALIGN(conv_surface->dst_data.surf_stride, atom_size);
+	}
+
+	ret = dla_read_input_address(&conv_surface->src_data, &input_address,
+					group->op_desc->index,
+					group->roi_index,
+					map_img_fmt[conv_op->data_format][1]);
+	if (ret)
+		goto exit;
+
+	CHECK_ALIGN(input_address, atom_size);
+
+	ASSERT_GOTO((conv_op->out_cvt.scale  == 1),
+		ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((conv_op->out_cvt.offset == 0),
+		ret, ERR(INVALID_INPUT), exit);
+
+	/* check if the register group is idle */
+	reg = cacc_reg_read(S_STATUS);
+	mask = group->id ? MASK(CACC_S_STATUS_0, STATUS_1) :
+		MASK(CACC_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CACC_S_STATUS_0, STATUS_1) :
+		SHIFT(CACC_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CACC_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = cmac_a_reg_read(S_STATUS);
+	mask = group->id ? MASK(CMAC_A_S_STATUS_0, STATUS_1) :
+        MASK(CMAC_A_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CMAC_A_S_STATUS_0, STATUS_1) :
+		SHIFT(CMAC_A_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CMAC_A_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = cmac_b_reg_read(S_STATUS);
+	mask = group->id ? MASK(CMAC_B_S_STATUS_0, STATUS_1) :
+		MASK(CMAC_B_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CMAC_B_S_STATUS_0, STATUS_1) :
+		SHIFT(CMAC_B_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CMAC_B_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = csc_reg_read(S_STATUS);
+	mask = group->id ? MASK(CSC_S_STATUS_0, STATUS_1) :
+		MASK(CSC_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CSC_S_STATUS_0, STATUS_1) :
+		SHIFT(CSC_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CSC_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = cdma_reg_read(S_STATUS);
+	mask = group->id ? MASK(CDMA_S_STATUS_0, STATUS_1) :
+		MASK(CDMA_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CDMA_S_STATUS_0, STATUS_1) :
+		SHIFT(CDMA_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CDMA_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	/* reverse config each sub-module in CC */
+
+	/* CACC */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CACC_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CACC_D_MISC_CFG_0, PROC_PRECISION));
+	cacc_reg_write(D_MISC_CFG, reg);
+
+	reg = ((conv_surface->dst_data.width - 1)
+		<< SHIFT(CACC_D_DATAOUT_SIZE_0_0, DATAOUT_WIDTH)) |
+		((conv_surface->dst_data.height - 1)
+		<< SHIFT(CACC_D_DATAOUT_SIZE_0_0, DATAOUT_HEIGHT));
+	cacc_reg_write(D_DATAOUT_SIZE_0, reg);
+
+	reg = ((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CACC_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
+	cacc_reg_write(D_DATAOUT_SIZE_1, reg);
+
+	low = LOW32BITS(output_address);
+	cacc_reg_write(D_DATAOUT_ADDR, low);
+	cacc_reg_write(D_BATCH_NUMBER, conv_op->batch - 1);
+	cacc_reg_write(D_LINE_STRIDE, conv_surface->dst_data.line_stride);
+	cacc_reg_write(D_SURF_STRIDE, conv_surface->dst_data.surf_stride);
+
+	if (conv_surface->dst_data.width == 1 &&
+				conv_surface->dst_data.height == 1) {
+		ASSERT_GOTO((((uint32_t)conv_surface->dst_data.line_stride ==
+			(uint32_t)(conv_surface->dst_data.width * atom_size))),
+			ret, ERR(INVALID_INPUT), exit);
+		reg = (CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, LINE_PACKED));
+		reg |= (CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, SURF_PACKED));
+	} else {
+		reg = (FIELD_ENUM(CACC_D_DATAOUT_MAP_0, LINE_PACKED, FALSE) <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, LINE_PACKED));
+		reg |= (FIELD_ENUM(CACC_D_DATAOUT_MAP_0, SURF_PACKED, FALSE) <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, SURF_PACKED));
+	}
+	cacc_reg_write(D_DATAOUT_MAP, reg);
+
+	cacc_reg_write(D_CLIP_CFG, conv_op->out_cvt.truncate);
+
+	/* CMAC */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CMAC_A_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CMAC_A_D_MISC_CFG_0, PROC_PRECISION));
+	cmac_a_reg_write(D_MISC_CFG, reg);
+	cmac_b_reg_write(D_MISC_CFG, reg);
+
+	/* CSC */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CSC_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CSC_D_MISC_CFG_0, IN_PRECISION)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CSC_D_MISC_CFG_0, PROC_PRECISION)) |
+		(conv_op->data_reuse
+		<< SHIFT(CSC_D_MISC_CFG_0, DATA_REUSE)) |
+		(conv_op->weight_reuse
+		<< SHIFT(CSC_D_MISC_CFG_0, WEIGHT_REUSE)) |
+		(conv_op->skip_data_rls
+		<< SHIFT(CSC_D_MISC_CFG_0, SKIP_DATA_RLS)) |
+		(conv_op->skip_weight_rls
+		<< SHIFT(CSC_D_MISC_CFG_0, SKIP_WEIGHT_RLS));
+	csc_reg_write(D_MISC_CFG, reg);
+
+	reg = (get_in_format(conv_op->data_format) <<
+		SHIFT(CSC_D_DATAIN_FORMAT_0, DATAIN_FORMAT));
+	csc_reg_write(D_DATAIN_FORMAT, reg);
+
+	reg = ((conv_op->input_width_csc - 1)
+		<< SHIFT(CSC_D_DATAIN_SIZE_EXT_0_0, DATAIN_WIDTH_EXT)) |
+		((conv_op->input_height_csc - 1)
+		<< SHIFT(CSC_D_DATAIN_SIZE_EXT_0_0, DATAIN_HEIGHT_EXT));
+	csc_reg_write(D_DATAIN_SIZE_EXT_0, reg);
+
+	reg = ((conv_op->input_channel_csc - 1)
+		<< SHIFT(CSC_D_DATAIN_SIZE_EXT_1_0, DATAIN_CHANNEL_EXT));
+	csc_reg_write(D_DATAIN_SIZE_EXT_1, reg);
+
+	reg = ((conv_op->batch - 1)
+		<< SHIFT(CSC_D_BATCH_NUMBER_0, BATCHES));
+	csc_reg_write(D_BATCH_NUMBER, reg);
+	reg = ((conv_op->post_extension)
+		<< SHIFT(CSC_D_POST_Y_EXTENSION_0, Y_EXTENSION));
+	csc_reg_write(D_POST_Y_EXTENSION, reg);
+
+	reg = ((conv_op->entry_per_slice - 1)
+		<< SHIFT(CSC_D_ENTRY_PER_SLICE_0, ENTRIES));
+	csc_reg_write(D_ENTRY_PER_SLICE, reg);
+
+	reg = (map_weight_fmt[conv_op->weight_format]
+		<< SHIFT(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT));
+	csc_reg_write(D_WEIGHT_FORMAT, reg);
+
+	reg = ((conv_op->kernel_width_csc - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_0_0, WEIGHT_WIDTH_EXT)) |
+		((conv_op->kernel_height_csc - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_0_0, WEIGHT_HEIGHT_EXT));
+	csc_reg_write(D_WEIGHT_SIZE_EXT_0, reg);
+
+	reg = ((conv_op->kernel_channel_csc - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_1_0, WEIGHT_CHANNEL_EXT)) |
+		((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_1_0, WEIGHT_KERNEL));
+	csc_reg_write(D_WEIGHT_SIZE_EXT_1, reg);
+
+	csc_reg_write(D_WEIGHT_BYTES, conv_surface->weight_data.size);
+	csc_reg_write(D_WMB_BYTES, conv_surface->wmb_data.size);
+
+	reg = ((conv_op->input_width_cmac - 1)
+		<< SHIFT(CSC_D_DATAOUT_SIZE_0_0, DATAOUT_WIDTH)) |
+		((conv_op->input_height_cmac - 1)
+		<< SHIFT(CSC_D_DATAOUT_SIZE_0_0, DATAOUT_HEIGHT));
+	csc_reg_write(D_DATAOUT_SIZE_0, reg);
+
+	reg = ((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CSC_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
+	csc_reg_write(D_DATAOUT_SIZE_1, reg);
+
+	reg = ((conv_surface->dst_data.width *
+				conv_surface->dst_data.height - 1)
+		<< SHIFT(CSC_D_ATOMICS_0, ATOMICS));
+	csc_reg_write(D_ATOMICS, reg);
+	reg = ((conv_op->release - 1)
+		<< SHIFT(CSC_D_RELEASE_0, RLS_SLICES));
+	csc_reg_write(D_RELEASE, reg);
+
+	if (conv_op->conv_mode == CONV_MODE_DIRECT) {
+		stride_x = conv_op->conv_stride_x - 1;
+		stride_y = conv_op->conv_stride_y - 1;
+		pad_x = conv_op->pad_x_left;
+		pad_y = conv_op->pad_y_top;
+	} else {
+		stride_x = 0;
+		stride_y = 0;
+		pad_x = 0;
+		pad_y = 0;
+	}
+
+	reg = (stride_x
+		<< SHIFT(CSC_D_CONV_STRIDE_EXT_0, CONV_X_STRIDE_EXT)) |
+		(stride_y
+		<< SHIFT(CSC_D_CONV_STRIDE_EXT_0, CONV_Y_STRIDE_EXT));
+	csc_reg_write(D_CONV_STRIDE_EXT, reg);
+
+	reg = ((conv_op->dilation_x - 1)
+		<< SHIFT(CSC_D_DILATION_EXT_0, X_DILATION_EXT)) |
+		((conv_op->dilation_y - 1)
+		<< SHIFT(CSC_D_DILATION_EXT_0, Y_DILATION_EXT));
+	csc_reg_write(D_DILATION_EXT, reg);
+
+	reg = (pad_x
+		<< SHIFT(CSC_D_ZERO_PADDING_0, PAD_LEFT)) |
+		(pad_y
+		<< SHIFT(CSC_D_ZERO_PADDING_0, PAD_TOP));
+	csc_reg_write(D_ZERO_PADDING, reg);
+
+	reg = (conv_op->pad_val
+		<< SHIFT(CSC_D_ZERO_PADDING_VALUE_0, PAD_VALUE)) &
+		MASK(CSC_D_ZERO_PADDING_VALUE_0, PAD_VALUE);
+	csc_reg_write(D_ZERO_PADDING_VALUE, reg);
+
+	reg = ((conv_op->data_bank - 1)
+		<< SHIFT(CSC_D_BANK_0, DATA_BANK)) |
+		((conv_op->weight_bank - 1)
+		<< SHIFT(CSC_D_BANK_0, WEIGHT_BANK));
+	csc_reg_write(D_BANK, reg);
+	csc_reg_write(D_PRA_CFG, conv_op->pra_truncate);
+
+	/* CBUF */
+	/* there's no CBUF register */
+
+	/* CDMA */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CDMA_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->in_precision]
+		<< SHIFT(CDMA_D_MISC_CFG_0, IN_PRECISION)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CDMA_D_MISC_CFG_0, PROC_PRECISION)) |
+		(conv_op->data_reuse
+		<< SHIFT(CDMA_D_MISC_CFG_0, DATA_REUSE)) |
+		(conv_op->weight_reuse
+		<< SHIFT(CDMA_D_MISC_CFG_0, WEIGHT_REUSE)) |
+		(conv_op->skip_data_rls
+		<< SHIFT(CDMA_D_MISC_CFG_0, SKIP_DATA_RLS)) |
+		(conv_op->skip_weight_rls
+		<< SHIFT(CDMA_D_MISC_CFG_0, SKIP_WEIGHT_RLS));
+	cdma_reg_write(D_MISC_CFG, reg);
+
+	reg = (get_in_format(conv_op->data_format) <<
+		SHIFT(CDMA_D_DATAIN_FORMAT_0, DATAIN_FORMAT)) |
+		(map_img_fmt[conv_op->data_format][0]
+		<< SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_FORMAT)) |
+		(map_pixel[conv_op->pixel_mapping]
+		<< SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_MAPPING)) |
+		(conv_op->pixel_override
+		<< SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_SIGN_OVERRIDE));
+	cdma_reg_write(D_DATAIN_FORMAT, reg);
+
+	reg = ((conv_surface->src_data.width - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_0_0, DATAIN_WIDTH)) |
+		((conv_surface->src_data.height - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_0_0, DATAIN_HEIGHT));
+	cdma_reg_write(D_DATAIN_SIZE_0, reg);
+
+	reg = ((conv_surface->src_data.channel - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_1_0, DATAIN_CHANNEL));
+	cdma_reg_write(D_DATAIN_SIZE_1, reg);
+
+	reg = ((conv_op->input_width_csc - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_EXT_0_0, DATAIN_WIDTH_EXT)) |
+		((conv_op->input_height_csc - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_EXT_0_0, DATAIN_HEIGHT_EXT));
+	cdma_reg_write(D_DATAIN_SIZE_EXT_0, reg);
+
+	reg = (map_ram[conv_surface->src_data.type]
+		<< SHIFT(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE));
+	cdma_reg_write(D_DAIN_RAM_TYPE, reg);
+
+	high = HIGH32BITS(input_address);
+	low = LOW32BITS(input_address);
+	cdma_reg_write(D_DAIN_ADDR_HIGH_0, high);
+	cdma_reg_write(D_DAIN_ADDR_LOW_0, low);
+
+	high = HIGH32BITS((input_address + conv_surface->offset_u));
+	low = LOW32BITS(input_address + conv_surface->offset_u);
+	cdma_reg_write(D_DAIN_ADDR_HIGH_1, high);
+	cdma_reg_write(D_DAIN_ADDR_LOW_1, low);
+
+	cdma_reg_write(D_LINE_STRIDE, conv_surface->src_data.line_stride);
+	cdma_reg_write(D_SURF_STRIDE, conv_surface->src_data.surf_stride);
+	cdma_reg_write(D_LINE_UV_STRIDE, conv_surface->in_line_uv_stride);
+
+	reg = ((conv_surface->src_data.line_stride ==
+			((uint32_t)conv_surface->src_data.width * atom_size))
+		<< SHIFT(CDMA_D_DAIN_MAP_0, LINE_PACKED));
+	reg |= ((conv_surface->src_data.surf_stride ==
+			((uint32_t)(conv_surface->src_data.width *
+			conv_surface->src_data.height) * atom_size))
+		<< SHIFT(CDMA_D_DAIN_MAP_0, SURF_PACKED));
+	cdma_reg_write(D_DAIN_MAP, reg);
+
+	reg = ((conv_op->batch - 1)
+		<< SHIFT(CDMA_D_BATCH_NUMBER_0, BATCHES));
+	cdma_reg_write(D_BATCH_NUMBER, reg);
+
+	cdma_reg_write(D_BATCH_STRIDE, conv_op->batch_stride);
+
+	reg = ((conv_op->entry_per_slice - 1)
+		<< SHIFT(CDMA_D_ENTRY_PER_SLICE_0, ENTRIES));
+	cdma_reg_write(D_ENTRY_PER_SLICE, reg);
+
+	reg = ((conv_op->fetch_grain - 1)
+		<< SHIFT(CDMA_D_FETCH_GRAIN_0, GRAINS));
+	cdma_reg_write(D_FETCH_GRAIN, reg);
+
+	reg = (map_weight_fmt[conv_op->weight_format]
+		<< SHIFT(CDMA_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT));
+	cdma_reg_write(D_WEIGHT_FORMAT, reg);
+
+	reg = ((conv_op->bytes_per_kernel - 1)
+		<< SHIFT(CDMA_D_WEIGHT_SIZE_0_0, BYTE_PER_KERNEL));
+	cdma_reg_write(D_WEIGHT_SIZE_0, reg);
+
+	reg = ((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CDMA_D_WEIGHT_SIZE_1_0, WEIGHT_KERNEL));
+	cdma_reg_write(D_WEIGHT_SIZE_1, reg);
+
+	reg = (map_ram[conv_surface->weight_data.type]
+		<< SHIFT(CDMA_D_WEIGHT_RAM_TYPE_0, WEIGHT_RAM_TYPE));
+	cdma_reg_write(D_WEIGHT_RAM_TYPE, reg);
+
+	high = HIGH32BITS(weight_address);
+	low = LOW32BITS(weight_address);
+	cdma_reg_write(D_WEIGHT_ADDR_HIGH, high);
+	cdma_reg_write(D_WEIGHT_ADDR_LOW, low);
+	cdma_reg_write(D_WEIGHT_BYTES, conv_surface->weight_data.size);
+
+	if (conv_op->weight_format == WEIGHT_FORMAT_COMPRESSED) {
+		high = HIGH32BITS(wgs_address);
+		low = LOW32BITS(wgs_address);
+		cdma_reg_write(D_WGS_ADDR_HIGH, high);
+		cdma_reg_write(D_WGS_ADDR_LOW, low);
+
+		high = HIGH32BITS(wmb_address);
+		low = LOW32BITS(wmb_address);
+		cdma_reg_write(D_WMB_ADDR_HIGH, high);
+		cdma_reg_write(D_WMB_ADDR_LOW, low);
+		cdma_reg_write(D_WMB_BYTES, conv_surface->wmb_data.size);
+	}
+
+	reg = (map_mean[conv_op->mean_format]
+		<< SHIFT(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT));
+	cdma_reg_write(D_MEAN_FORMAT, reg);
+
+	if (conv_op->mean_format == MEAN_FORMAT_ENABLE) {
+		reg = ((conv_op->mean_ry
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_0_0, MEAN_RY)) &
+			MASK(CDMA_D_MEAN_GLOBAL_0_0, MEAN_RY)) |
+			((conv_op->mean_gu
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_0_0, MEAN_GU)) &
+			MASK(CDMA_D_MEAN_GLOBAL_0_0, MEAN_GU));
+		cdma_reg_write(D_MEAN_GLOBAL_0, reg);
+
+		reg = ((conv_op->mean_bv
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_1_0, MEAN_BV))&
+			MASK(CDMA_D_MEAN_GLOBAL_1_0, MEAN_BV)) |
+			((conv_op->mean_ax
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_1_0, MEAN_AX))&
+			MASK(CDMA_D_MEAN_GLOBAL_1_0, MEAN_AX));
+		cdma_reg_write(D_MEAN_GLOBAL_1, reg);
+	}
+
+	if (conv_op->in_cvt.enable) {
+		reg = ((FIELD_ENUM(CDMA_D_CVT_CFG_0, CVT_EN, ENABLE))
+			<< SHIFT(CDMA_D_CVT_CFG_0, CVT_EN)) |
+			(conv_op->in_cvt.truncate
+			<< SHIFT(CDMA_D_CVT_CFG_0, CVT_TRUNCATE));
+		cdma_reg_write(D_CVT_CFG, reg);
+		cdma_reg_write(D_CVT_OFFSET, conv_op->in_cvt.offset);
+		cdma_reg_write(D_CVT_SCALE, conv_op->in_cvt.scale);
+	} else {
+		reg = ((FIELD_ENUM(CDMA_D_CVT_CFG_0, CVT_EN, DISABLE))
+			<< SHIFT(CDMA_D_CVT_CFG_0, CVT_EN));
+		cdma_reg_write(D_CVT_CFG, reg);
+	}
+
+	reg = ((conv_op->conv_stride_x - 1)
+		<< SHIFT(CDMA_D_CONV_STRIDE_0, CONV_X_STRIDE)) |
+		((conv_op->conv_stride_y - 1)
+		<< SHIFT(CDMA_D_CONV_STRIDE_0, CONV_Y_STRIDE));
+	cdma_reg_write(D_CONV_STRIDE, reg);
+
+	reg = (conv_op->pad_x_left <<
+		SHIFT(CDMA_D_ZERO_PADDING_0, PAD_LEFT)) |
+		(conv_op->pad_x_right
+		<< SHIFT(CDMA_D_ZERO_PADDING_0, PAD_RIGHT)) |
+		(conv_op->pad_y_top
+		<< SHIFT(CDMA_D_ZERO_PADDING_0, PAD_TOP)) |
+		(conv_op->pad_y_bottom
+		<< SHIFT(CDMA_D_ZERO_PADDING_0, PAD_BOTTOM));
+	cdma_reg_write(D_ZERO_PADDING,   reg);
+
+	reg = conv_op->pad_val <<
+		SHIFT(CDMA_D_ZERO_PADDING_VALUE_0, PAD_VALUE) &
+		MASK(CDMA_D_ZERO_PADDING_VALUE_0, PAD_VALUE);
+	cdma_reg_write(D_ZERO_PADDING_VALUE, reg);
+	reg = ((conv_op->weight_bank - 1)
+		<< SHIFT(CDMA_D_BANK_0, WEIGHT_BANK)) |
+		((conv_op->data_bank - 1)
+		<< SHIFT(CDMA_D_BANK_0, DATA_BANK));
+	cdma_reg_write(D_BANK, reg);
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_conv_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group)
+{
+	return 1;
+}
+
+void
+dla_conv_dump_config(struct dla_processor_group *group)
+{
+	struct dla_conv_op_desc *conv_op;
+	struct dla_conv_surface_desc *conv_surface;
+
+	conv_surface = &group->surface_desc->conv_surface;
+	conv_op = &group->operation_desc->conv_op;
+
+	dla_debug_conv_surface_desc(conv_surface, group->roi_index);
+	dla_debug_conv_op_desc(conv_op, group->roi_index);
+}
+
+int
+dla_conv_program(struct dla_processor_group *group)
+{
+	int32_t ret;
+
+	dla_trace("Enter: %s", __func__);
+
+	ret = processor_conv_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/dla_engine_internal.h b/drivers/nvdla/dla_engine_internal.h
new file mode 100644
index 000000000000..d29c7b4c56c3
--- /dev/null
+++ b/drivers/nvdla/dla_engine_internal.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_ENGINE_INTERNAL_H_
+#define __FIRMWARE_DLA_ENGINE_INTERNAL_H_
+
+#include <opendla.h>
+#include <dla_engine.h>
+#include <dla_interface.h>
+#include <dla_debug.h>
+
+#include "nvdla_interface.h"
+
+#define BITS(num, range) ((((0xFFFFFFFF >> (31 - (1 ? range))) & \
+			(0xFFFFFFFF << (0 ? range))) & num) >> \
+			(0 ? range))
+#define HIGH32BITS(val64bit) ((uint32_t)(val64bit >> 32))
+#define LOW32BITS(val64bit) ((uint32_t)(val64bit))
+
+#ifdef MIN
+#undef MIN
+#endif /* MIN */
+
+#ifdef MAX
+#undef MAX
+#endif /* MAX */
+
+#define MIN(a, b) ((a) > (b) ? (b) : (a))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+
+/*********************************************************/
+/******************** Utilities **************************/
+/*********************************************************/
+#ifdef DEBUG
+#define CHECK_ALIGN(val, align)		 assert((val&(align-1)) == 0)
+#else
+#define CHECK_ALIGN(val, align)
+#endif /* DEBUG */
+
+#define MASK(reg, field)		(reg##_##field##_FIELD)
+#define FIELD_ENUM(r, f, e)		(r##_##f##_##e)
+#define SHIFT(reg, field)		(reg##_##field##_SHIFT)
+
+#define GLB_REG(name)                GLB_##name##_0
+#define MCIF_REG(name)               MCIF_##name##_0
+#define CVIF_REG(name)               CVIF_##name##_0
+#define BDMA_REG(name)               BDMA_##name##_0
+#define CDMA_REG(name)               CDMA_##name##_0
+#define CSC_REG(name)                CSC_##name##_0
+#define CMAC_A_REG(name)             CMAC_A_##name##_0
+#define CMAC_B_REG(name)             CMAC_B_##name##_0
+#define CACC_REG(name)               CACC_##name##_0
+#define SDP_RDMA_REG(name)           SDP_RDMA_##name##_0
+#define SDP_REG(name)                SDP_##name##_0
+#define PDP_RDMA_REG(name)           PDP_RDMA_##name##_0
+#define PDP_REG(name)                PDP_##name##_0
+#define CDP_RDMA_REG(name)           CDP_RDMA_##name##_0
+#define CDP_REG(name)                CDP_##name##_0
+#define RBK_REG(name)                RBK_##name##_0
+
+/* alias for register read for each sub-module */
+#define glb_reg_read(reg)           reg_read(GLB_REG(reg))
+#define bdma_reg_read(reg)          reg_read(BDMA_REG(reg))
+#define cdma_reg_read(reg)          reg_read(CDMA_REG(reg))
+#define csc_reg_read(reg)           reg_read(CSC_REG(reg))
+#define cmac_a_reg_read(reg)        reg_read(CMAC_A_REG(reg))
+#define cmac_b_reg_read(reg)        reg_read(CMAC_B_REG(reg))
+#define cacc_reg_read(reg)          reg_read(CACC_REG(reg))
+#define sdp_rdma_reg_read(reg)      reg_read(SDP_RDMA_REG(reg))
+#define sdp_reg_read(reg)           reg_read(SDP_REG(reg))
+#define pdp_rdma_reg_read(reg)      reg_read(PDP_RDMA_REG(reg))
+#define pdp_reg_read(reg)           reg_read(PDP_REG(reg))
+#define cdp_rdma_reg_read(reg)      reg_read(CDP_RDMA_REG(reg))
+#define cdp_reg_read(reg)           reg_read(CDP_REG(reg))
+#define rubik_reg_read(reg)         reg_read(RBK_REG(reg))
+
+/* alias for register write for each sub-module */
+#define glb_reg_write(reg, val)      reg_write(GLB_REG(reg), val)
+#define bdma_reg_write(reg, val)     reg_write(BDMA_REG(reg), val)
+#define cdma_reg_write(reg, val)     reg_write(CDMA_REG(reg), val)
+#define csc_reg_write(reg, val)      reg_write(CSC_REG(reg), val)
+#define cmac_a_reg_write(reg, val)   reg_write(CMAC_A_REG(reg), val)
+#define cmac_b_reg_write(reg, val)   reg_write(CMAC_B_REG(reg), val)
+#define cacc_reg_write(reg, val)     reg_write(CACC_REG(reg), val)
+#define sdp_rdma_reg_write(reg, val) reg_write(SDP_RDMA_REG(reg), val)
+#define sdp_reg_write(reg, val)      reg_write(SDP_REG(reg), val)
+#define pdp_rdma_reg_write(reg, val) reg_write(PDP_RDMA_REG(reg), val)
+#define pdp_reg_write(reg, val)      reg_write(PDP_REG(reg), val)
+#define cdp_rdma_reg_write(reg, val) reg_write(CDP_RDMA_REG(reg), val)
+#define cdp_reg_write(reg, val)      reg_write(CDP_REG(reg), val)
+#define rubik_reg_write(reg, val)    reg_write(RBK_REG(reg), val)
+
+void reg_write(uint32_t addr, uint32_t reg);
+uint32_t reg_read(uint32_t addr);
+
+/**
+ * Operation descriptor cache functions
+ */
+void
+dla_put_op_desc(struct dla_common_op_desc *op_desc);
+struct dla_common_op_desc
+*dla_get_op_desc(struct dla_task *task,
+			   int16_t index,
+			   uint8_t op_type,
+			   uint8_t roi_index);
+void
+dla_dump_op_desc(struct dla_common_op_desc *desc);
+void
+dla_get_refcount(struct dla_common_op_desc *op_desc);
+void
+dla_init_op_cache(struct dla_engine *engine);
+
+/**
+ * Operation completion handler
+ */
+int
+dla_op_completion(struct dla_processor *processor,
+		      struct dla_processor_group *group);
+
+int32_t
+dla_read_lut(struct dla_engine *engine, int16_t index, void *dst);
+int
+dla_enable_intr(uint32_t mask);
+int
+dla_disable_intr(uint32_t mask);
+int
+utils_get_free_group(struct dla_processor *processor,
+			uint8_t *group_id,
+			uint8_t *rdma_id);
+int32_t
+dla_get_dma_cube_address(void *driver_context,
+						void *task_data,
+						int16_t index,
+						uint32_t offset,
+						void *dst_ptr,
+						uint32_t destination);
+int
+dla_read_input_address(struct dla_data_cube *data,
+		       uint64_t *address,
+		       int16_t op_index,
+		       uint8_t roi_index,
+		       uint8_t bpp);
+
+/**
+ * BDMA operations
+ */
+void
+dla_bdma_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_bdma_enable(struct dla_processor_group *group);
+int
+dla_bdma_program(struct dla_processor_group *group);
+int
+dla_bdma_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group);
+void
+dla_bdma_dump_config(struct dla_processor_group *group);
+void
+dla_bdma_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_bdma_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_bdma_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_bdma_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_bdma_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * Convolution operations
+ */
+void
+dla_conv_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_conv_enable(struct dla_processor_group *group);
+int
+dla_conv_program(struct dla_processor_group *group);
+int
+dla_conv_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group);
+void
+dla_conv_dump_config(struct dla_processor_group *group);
+void
+dla_conv_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_conv_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_conv_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_conv_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_conv_dump_stat(struct dla_processor *processor) {}
+#endif /* STAT_ENABLE */
+
+/**
+ * SDP operations
+ */
+void
+dla_sdp_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_sdp_enable(struct dla_processor_group *group);
+int
+dla_sdp_program(struct dla_processor_group *group);
+int
+dla_sdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group);
+void
+dla_sdp_dump_config(struct dla_processor_group *group);
+void
+dla_sdp_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_sdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_sdp_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_sdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_sdp_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * PDP operations
+ */
+void
+dla_pdp_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_pdp_enable(struct dla_processor_group *group);
+int
+dla_pdp_program(struct dla_processor_group *group);
+int
+dla_pdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group);
+void
+dla_pdp_dump_config(struct dla_processor_group *group);
+void
+dla_pdp_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_pdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_pdp_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_pdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_pdp_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * CDP operations
+ */
+void
+dla_cdp_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_cdp_enable(struct dla_processor_group *group);
+int
+dla_cdp_program(struct dla_processor_group *group);
+int
+dla_cdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group);
+void
+dla_cdp_dump_config(struct dla_processor_group *group);
+void
+dla_cdp_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_cdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_cdp_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_cdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_cdp_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * RUBIK operations
+ */
+void
+dla_rubik_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_rubik_enable(struct dla_processor_group *group);
+int
+dla_rubik_program(struct dla_processor_group *group);
+int
+dla_rubik_is_ready(struct dla_processor *processor,
+			     struct dla_processor_group *group);
+void
+dla_rubik_dump_config(struct dla_processor_group *group);
+void
+dla_rubik_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_rubik_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_rubik_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_rubik_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_rubik_dump_stat(struct dla_processor *processor) {}
+#endif
+
+#endif
diff --git a/drivers/nvdla/engine.c b/drivers/nvdla/engine.c
new file mode 100644
index 000000000000..904cca54f877
--- /dev/null
+++ b/drivers/nvdla/engine.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+#include "common.h"
+
+static const uint32_t map_rdma_ptr_addr[] = {
+	0xFFFFFFFF,
+	0xFFFFFFFF,
+	SDP_REG(RDMA_S_POINTER),
+	PDP_REG(RDMA_S_POINTER),
+	CDP_REG(RDMA_S_POINTER),
+	0xFFFFFFFF,
+};
+
+static const uint32_t map_sts_addr[] = {
+	BDMA_REG(STATUS),
+	CACC_REG(S_STATUS),
+	SDP_REG(S_STATUS),
+	PDP_REG(S_STATUS),
+	CDP_REG(S_STATUS),
+	RBK_REG(S_STATUS),
+};
+
+static const uint32_t map_ptr_addr[] = {
+	BDMA_REG(STATUS),
+	CACC_REG(S_POINTER),
+	SDP_REG(S_POINTER),
+	PDP_REG(S_POINTER),
+	CDP_REG(S_POINTER),
+	RBK_REG(S_POINTER),
+};
+
+int32_t dla_enable_intr(uint32_t mask)
+{
+	uint32_t reg = glb_reg_read(S_INTR_MASK);
+
+	reg = reg & (~mask);
+	glb_reg_write(S_INTR_MASK, reg);
+
+	RETURN(0);
+}
+
+int32_t dla_disable_intr(uint32_t mask)
+{
+	uint32_t reg = glb_reg_read(S_INTR_MASK);
+
+	reg = reg | mask;
+	glb_reg_write(S_INTR_MASK, reg);
+
+	RETURN(0);
+}
+
+uint8_t bdma_grp_sts[2] = {
+	FIELD_ENUM(BDMA_STATUS_0, IDLE, YES),
+	FIELD_ENUM(BDMA_STATUS_0, IDLE, YES)
+};
+
+struct dla_roi_desc roi_desc;
+
+/**
+ * Get DMA data cube address
+ */
+int32_t
+dla_get_dma_cube_address(void *driver_context, void *task_data,
+					int16_t index, uint32_t offset, void *dst_ptr,
+					uint32_t destination)
+{
+	int32_t ret = 0;
+	uint64_t *pdst = (uint64_t *)dst_ptr;
+       ret = dla_get_dma_address(driver_context, task_data, index,
+								dst_ptr, destination);
+	if (ret)
+		goto exit;
+
+	pdst[0] += offset;
+
+exit:
+	return ret;
+}
+
+/**
+ * Read input buffer address
+ *
+ * For input layer, in case of static ROI this address is read
+ * from address list and index is specified in data cube. In case
+ * dynamic ROI, it has to be read depending on ROI information
+ * and using surface address
+ *
+ * For all other layers, this address is read from address list
+ * using index specified in data cube
+ */
+int
+dla_read_input_address(struct dla_data_cube *data,
+		       uint64_t *address,
+		       int16_t op_index,
+		       uint8_t roi_index,
+		       uint8_t bpp)
+{
+	uint64_t roi_desc_addr;
+	int32_t ret = ERR(INVALID_INPUT);
+	struct dla_engine *en = dla_get_engine();
+
+	/**
+	 * If memory type is HW then no address required
+	 */
+	if (data->type == DLA_MEM_HW) {
+		ret = 0;
+		goto exit;
+	}
+
+	/**
+	 * If address list index is not -1 means this address has to
+	 * be read from address list
+	 */
+	if (data->address != -1) {
+
+		/**
+		 * But if other parameters indicate that this is input layer
+		 * for dynamic ROI then it is an error
+		 */
+		if (en->network->dynamic_roi &&
+			en->network->input_layer == op_index)
+			goto exit;
+		ret = dla_get_dma_cube_address(en->driver_context,
+						en->task->task_data,
+						data->address,
+						data->offset,
+						(void *)address,
+						DESTINATION_DMA);
+		goto exit;
+	}
+
+	/**
+	 * Check if it is dynamic ROI and this is input layer
+	 */
+	if (en->network->dynamic_roi && en->network->input_layer == op_index) {
+		if (!en->task->surface_addr)
+			goto exit;
+
+		/* Calculate address of ROI descriptor in array */
+		roi_desc_addr = en->task->roi_array_addr;
+
+		/* Read ROI descriptor */
+		ret = dla_data_read(en->driver_context,
+				en->task->task_data,
+				roi_desc_addr,
+				(void *)&roi_desc,
+				sizeof(roi_desc),
+				sizeof(struct dla_roi_array_desc) +
+				roi_index * sizeof(struct dla_roi_desc));
+		if (ret)
+			goto exit;
+
+		/* Calculate ROI address */
+		*address = en->task->surface_addr;
+		*address += (roi_desc.top * data->line_stride) +
+						(bpp * roi_desc.left);
+	}
+
+exit:
+	RETURN(ret);
+}
+
+int
+utils_get_free_group(struct dla_processor *processor,
+		     uint8_t *group_id,
+		     uint8_t *rdma_id)
+{
+	int32_t ret = 0;
+	uint32_t pointer;
+	uint32_t hw_consumer_ptr;
+	uint32_t hw_rdma_ptr;
+
+	hw_rdma_ptr = 0;
+
+	if (processor->op_type == DLA_OP_BDMA) {
+		pointer = reg_read(map_ptr_addr[processor->op_type]);
+		hw_consumer_ptr = ((pointer & MASK(BDMA_STATUS_0, GRP0_BUSY)) >>
+				SHIFT(BDMA_STATUS_0, GRP0_BUSY)) ==
+				FIELD_ENUM(BDMA_STATUS_0, GRP0_BUSY, YES) ?
+				1 : 0;
+	} else {
+		pointer = reg_read(map_ptr_addr[processor->op_type]);
+		hw_consumer_ptr = (pointer & MASK(CDP_S_POINTER_0, CONSUMER)) >>
+				SHIFT(CDP_S_POINTER_0, CONSUMER);
+
+		/**
+		 * Read current consumer pointer for RDMA only if processor
+		 * has RDMA module
+		 */
+		if (map_rdma_ptr_addr[processor->op_type] != 0xFFFFFFFF) {
+			pointer =
+			reg_read(map_rdma_ptr_addr[processor->op_type]);
+			hw_rdma_ptr = (pointer &
+					MASK(CDP_S_POINTER_0, CONSUMER)) >>
+					SHIFT(CDP_S_POINTER_0, CONSUMER);
+		}
+	}
+
+	/**
+	 * If both processors are programmed then exit
+	 */
+	if (processor->group_status == 0x3) {
+		ret = ERR(PROCESSOR_BUSY);
+		goto exit;
+	}
+
+	if (!processor->group_status)
+		/**
+		 * If both groups are idle then use consumer pointer
+		 */
+		*group_id = hw_consumer_ptr;
+	else
+		/**
+		 * Here it is assumed that only one group is idle or busy
+		 * and hence right shift will work to get correct
+		 * group id
+		 */
+		*group_id = !(processor->group_status >> 1);
+
+	/**
+	 * If both groups are idle then read group id from pointer
+	 */
+	if (!processor->rdma_status)
+		*rdma_id = hw_rdma_ptr;
+	else
+		*rdma_id = !(processor->rdma_status >> 1);
+
+exit:
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/engine_data.c b/drivers/nvdla/engine_data.c
new file mode 100644
index 000000000000..c967cffebb1a
--- /dev/null
+++ b/drivers/nvdla/engine_data.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <nvdla_interface.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+
+static union dla_operation_container operation_desc[DLA_OP_NUM][DLA_NUM_GROUPS];
+static union dla_surface_container surface_desc[DLA_OP_NUM][DLA_NUM_GROUPS];
+
+static struct dla_task global_task;
+
+static struct dla_engine engine = {
+	.processors[DLA_OP_BDMA] = {
+		.name = "BDMA",
+		.op_type = DLA_OP_BDMA,
+		.program = dla_bdma_program,
+		.enable = dla_bdma_enable,
+		.set_producer = dla_bdma_set_producer,
+		.is_ready = dla_bdma_is_ready,
+		.dump_config = dla_bdma_dump_config,
+		.rdma_check = dla_bdma_rdma_check,
+		.get_stat_data = dla_bdma_stat_data,
+		.dump_stat = dla_bdma_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_BDMA][0],
+			.surface_desc = &surface_desc[DLA_OP_BDMA][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_BDMA][1],
+			.surface_desc = &surface_desc[DLA_OP_BDMA][1],
+		},
+	},
+	.processors[DLA_OP_CONV] = {
+		.name = "Convolution",
+		.op_type = DLA_OP_CONV,
+		.program = dla_conv_program,
+		.enable = dla_conv_enable,
+		.set_producer = dla_conv_set_producer,
+		.is_ready = dla_conv_is_ready,
+		.dump_config = dla_conv_dump_config,
+		.rdma_check = dla_conv_rdma_check,
+		.get_stat_data = dla_conv_stat_data,
+		.dump_stat = dla_conv_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CONV][0],
+			.surface_desc = &surface_desc[DLA_OP_CONV][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CONV][1],
+			.surface_desc = &surface_desc[DLA_OP_CONV][1],
+		},
+	},
+	.processors[DLA_OP_SDP] = {
+		.name = "SDP",
+		.op_type = DLA_OP_SDP,
+		.program = dla_sdp_program,
+		.enable = dla_sdp_enable,
+		.set_producer = dla_sdp_set_producer,
+		.is_ready = dla_sdp_is_ready,
+		.dump_config = dla_sdp_dump_config,
+		.rdma_check = dla_sdp_rdma_check,
+		.get_stat_data = dla_sdp_stat_data,
+		.dump_stat = dla_sdp_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_SDP][0],
+			.surface_desc = &surface_desc[DLA_OP_SDP][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_SDP][1],
+			.surface_desc = &surface_desc[DLA_OP_SDP][1],
+		},
+	},
+	.processors[DLA_OP_PDP] = {
+		.name = "PDP",
+		.op_type = DLA_OP_PDP,
+		.program = dla_pdp_program,
+		.enable = dla_pdp_enable,
+		.set_producer = dla_pdp_set_producer,
+		.is_ready = dla_pdp_is_ready,
+		.dump_config = dla_pdp_dump_config,
+		.rdma_check = dla_pdp_rdma_check,
+		.get_stat_data = dla_pdp_stat_data,
+		.dump_stat = dla_pdp_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_PDP][0],
+			.surface_desc = &surface_desc[DLA_OP_PDP][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_PDP][1],
+			.surface_desc = &surface_desc[DLA_OP_PDP][1],
+		},
+	},
+	.processors[DLA_OP_CDP] = {
+		.name = "CDP",
+		.op_type = DLA_OP_CDP,
+		.program = dla_cdp_program,
+		.enable = dla_cdp_enable,
+		.set_producer = dla_cdp_set_producer,
+		.is_ready = dla_cdp_is_ready,
+		.dump_config = dla_cdp_dump_config,
+		.rdma_check = dla_cdp_rdma_check,
+		.get_stat_data = dla_cdp_stat_data,
+		.dump_stat = dla_cdp_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CDP][0],
+			.surface_desc = &surface_desc[DLA_OP_CDP][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CDP][1],
+			.surface_desc = &surface_desc[DLA_OP_CDP][1],
+		},
+	},
+
+	.processors[DLA_OP_RUBIK] = {
+		.name = "RUBIK",
+		.op_type = DLA_OP_RUBIK,
+		.program = dla_rubik_program,
+		.enable = dla_rubik_enable,
+		.set_producer = dla_rubik_set_producer,
+		.is_ready = dla_rubik_is_ready,
+		.dump_config = dla_rubik_dump_config,
+		.rdma_check = dla_rubik_rdma_check,
+		.get_stat_data = dla_rubik_stat_data,
+		.dump_stat = dla_rubik_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_RUBIK][0],
+			.surface_desc = &surface_desc[DLA_OP_RUBIK][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_RUBIK][1],
+			.surface_desc = &surface_desc[DLA_OP_RUBIK][1],
+		},
+	},
+
+};
+
+struct dla_engine *dla_get_engine(void)
+{
+	return &engine;
+}
+
+int32_t dla_register_driver(void **engine_context, void *driver_context)
+{
+	*engine_context = &engine;
+	engine.task = &global_task;
+	engine.driver_context = driver_context;
+	engine.task->task_data = NULL;
+
+	dla_init_op_cache(&engine);
+
+	RETURN(0);
+}
+
+uint32_t reg_read(uint32_t addr)
+{
+	return dla_reg_read(engine.driver_context, addr);
+}
+
+void reg_write(uint32_t addr, uint32_t reg)
+{
+	dla_reg_write(engine.driver_context, addr, reg);
+}
diff --git a/drivers/nvdla/engine_debug.c b/drivers/nvdla/engine_debug.c
new file mode 100644
index 000000000000..7ed4f0aebc6c
--- /dev/null
+++ b/drivers/nvdla/engine_debug.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dla_debug.h>
+#include <dla_interface.h>
+#include <dla_sched.h>
+
+#include "engine_debug.h"
+
+#if DEBUG_NETWORK_DATA
+
+void
+dla_debug_network_desc(struct dla_network_desc *nd)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW dla_network_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("op desc index      = %d\n", nd->operation_desc_index);
+	dla_debug("surface desc index = %d\n", nd->surface_desc_index);
+	dla_debug("dep graph index    = %d\n", nd->dependency_graph_index);
+	dla_debug("lut data index     = %d\n", nd->lut_data_index);
+	dla_debug("stat_list_index    = %d\n", nd->stat_list_index);
+	dla_debug("roi array index    = %d\n", nd->roi_array_index);
+	dla_debug("surface index      = %d\n", nd->surface_index);
+	dla_debug("num rois           = %u\n", nd->num_rois);
+	dla_debug("num ops            = %u\n", nd->num_operations);
+	dla_debug("num luts           = %u\n", nd->num_luts);
+	dla_debug("num addr           = %u\n", nd->num_addresses);
+	dla_debug("input layer        = %u\n", nd->input_layer);
+	dla_debug("dynamic roi        = %u\n", nd->dynamic_roi);
+}
+
+static void
+dla_debug_bdma_transfer(struct dla_bdma_transfer_desc *tr, int32_t id)
+{
+	dla_debug("transfer[%d]            = [ dla_bdma_transfer_desc =>\n", id);
+	dla_debug("    source_address      = %x\n", tr->source_address);
+	dla_debug("    destination_address = %x\n", tr->destination_address);
+	dla_debug("    line_size           = %x\n", tr->line_size);
+	dla_debug("    line_repeat         = %x\n", tr->line_repeat);
+	dla_debug("    source_line         = %x\n", tr->source_line);
+	dla_debug("    destination_line    = %x\n", tr->destination_line);
+	dla_debug("    surface_repeat      = %x\n", tr->surface_repeat);
+	dla_debug("    source_surface      = %x\n", tr->source_surface);
+	dla_debug("    destination_surface = %x\n", tr->destination_surface);
+}
+
+void
+dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi)
+{
+	int32_t i;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_bdma_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("source_type      = %u\n", desc->source_type);
+	dla_debug("destination_type = %u\n", desc->destination_type);
+	dla_debug("num_transfers    = %u\n", desc->num_transfers);
+	for (i = 0; i < desc->num_transfers; i++)
+		dla_debug_bdma_transfer(&desc->transfers[i], i);
+}
+
+void
+dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_bdma_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("num_transfers    = %u\n", desc->num_transfers);
+}
+
+void
+dla_debug_address_info(struct dla_task *tk)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW address list\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("task base address        = %llu\n", tk->base);
+	dla_debug("op desc address          = %llu\n", tk->operation_desc_addr);
+	dla_debug("surface desc address     = %llu\n", tk->surface_desc_addr);
+	dla_debug("dependency graph address = %llu\n", tk->dependency_graph_addr);
+	dla_debug("LUT data address         = %llu\n", tk->lut_data_addr);
+	dla_debug("stat address             = %llu\n", tk->stat_data_addr);
+	dla_debug("ROI array address        = %llu\n", tk->roi_array_addr);
+	dla_debug("surface address          = %llu\n", tk->surface_addr);
+}
+
+void
+dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi)
+{
+	int32_t i;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_common_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("[%p] Operation index %d ROI %d dep_count %d type %d\n",
+			(unsigned int *)desc, desc->index, desc->roi_index,
+			desc->dependency_count, desc->op_type);
+	dla_debug("consumers = [ dla_consumer =>\n");
+	for (i = 0; i < DLA_OP_NUM; i++)
+		dla_debug(" [ %d %d ]", desc->consumers[i].index,
+					desc->consumers[i].event);
+	dla_debug("]");
+	dla_debug("fused_parent = [ dla_consumer =>\n");
+	dla_debug(" [ %d %d ]", desc->fused_parent.index,
+					desc->fused_parent.event);
+	dla_debug("]");
+}
+
+static void
+dla_debug_data_cube(struct dla_data_cube *cube)
+{
+	dla_debug("    type          = %u\n", cube->type);
+	dla_debug("    address       = %d\n", cube->address);
+	dla_debug("    width         = %x\n", cube->width);
+	dla_debug("    height        = %x\n", cube->height);
+	dla_debug("    channel       = %x\n", cube->channel);
+	dla_debug("    size          = %u\n", cube->size);
+	dla_debug("    line_stride   = %u\n", cube->line_stride);
+	dla_debug("    surf_stride   = %u\n", cube->surf_stride);
+	dla_debug("    plane_stride  = %u\n", cube->plane_stride);
+	dla_debug("]");
+}
+
+static void
+dla_debug_converter(struct dla_cvt_param *cvt)
+{
+	dla_debug("[ scale = %d, truncate = %u, enable = %u, offset = %d ]\n",
+			cvt->scale, cvt->truncate, cvt->enable, cvt->offset);
+}
+
+static void
+dla_debug_float_data(struct dla_float_data *float_data)
+{
+	dla_debug("[ scale = %d, shifter = %d ]\n",
+			float_data->scale, float_data->shifter);
+}
+
+static void
+dla_debug_dla_slope(union dla_slope *slope)
+{
+	dla_debug("    data_i =\n");
+	dla_debug_float_data(&slope->data_i);
+	dla_debug("    data_f = %u\n", slope->data_f);
+}
+
+static void
+dla_debug_lut_offset(union dla_lut_offset *offset)
+{
+	dla_debug("    exp_offset = %d\n", offset->exp_offset);
+	dla_debug("    frac_bits  = %d\n", offset->frac_bits);
+}
+
+void
+dla_debug_lut_params(struct dla_lut_param *lut_param)
+{
+	int32_t i, j;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW dla_lut_param\n");
+	dla_debug("---------------------------------------------------------\n");
+
+	dla_debug("linear_exp_table            = [\n");
+	for (i = 0; i < (1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1; i++)
+		dla_debug(" %u", lut_param->linear_exp_table[i]);
+	dla_debug("]");
+
+	dla_debug("linear_only_table           = [\n");
+	for (j = 0; j < (1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1; j++)
+		dla_debug(" %u\n", lut_param->linear_only_table[j]);
+	dla_debug("]\n");
+
+	dla_debug("linear_exp_offset           =\n");
+	dla_debug_lut_offset(&lut_param->linear_exp_offset);
+	dla_debug("linear_only_offset          =\n");
+	dla_debug_lut_offset(&lut_param->linear_only_offset);
+	dla_debug("linear_exp_start            = %llu\n",
+				lut_param->linear_exp_start);
+	dla_debug("linear_exp_end            = %llu\n",
+				lut_param->linear_exp_end);
+	dla_debug("linear_only_start           = %llu\n",
+				lut_param->linear_only_start);
+	dla_debug("linear_only_end           = %llu\n",
+				lut_param->linear_only_end);
+	dla_debug("linear_exp_underflow_slope  =\n");
+	dla_debug_dla_slope(&lut_param->linear_exp_underflow_slope);
+	dla_debug("linear_exp_overflow_slope   =\n");
+	dla_debug_dla_slope(&lut_param->linear_exp_overflow_slope);
+	dla_debug("linear_only_underflow_slope =\n");
+	dla_debug_dla_slope(&lut_param->linear_only_underflow_slope);
+	dla_debug("linear_only_overflow_slope  =\n");
+	dla_debug_dla_slope(&lut_param->linear_only_overflow_slope);
+	dla_debug("hybrid_priority             = %u\n",
+				lut_param->hybrid_priority);
+	dla_debug("underflow_priority          = %u\n",
+				lut_param->underflow_priority);
+	dla_debug("overflow_priority           = %u\n",
+				lut_param->overflow_priority);
+	dla_debug("method                      = %u\n",
+				lut_param->method);
+}
+
+void
+dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_bdma_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("read_stall   = %u\n", stat->read_stall);
+	dla_debug("write_stall  = %u\n", stat->write_stall);
+	dla_debug("runtime      = %u\n", stat->runtime);
+}
+
+void
+dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_conv_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("weight_data         = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->weight_data);
+	dla_debug("wmb_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->wmb_data);
+	dla_debug("wgs_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->wgs_data);
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+	dla_debug("offset_u            = %lld\n", desc->offset_u);
+	dla_debug("in_line_uv_stride   = %u\n", desc->in_line_uv_stride);
+}
+
+void
+dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_conv_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("conv_mode          = %u\n", desc->conv_mode);
+	dla_debug("data_reuse         = %u\n", desc->data_reuse);
+	dla_debug("weight_reuse       = %u\n", desc->weight_reuse);
+	dla_debug("skip_data_rls      = %u\n", desc->skip_data_rls);
+	dla_debug("skip_weight_rls    = %u\n", desc->skip_weight_rls);
+	dla_debug("entry_per_slice    = %u\n", desc->entry_per_slice);
+	dla_debug("data_format        = %u\n", desc->data_format);
+	dla_debug("pixel_mapping      = %u\n", desc->pixel_mapping);
+	dla_debug("fetch_grain        = %u\n", desc->fetch_grain);
+	dla_debug("batch              = %u\n", desc->batch);
+	dla_debug("weight_format      = %u\n", desc->weight_format);
+	dla_debug("data_bank          = %u\n", desc->data_bank);
+	dla_debug("weight_bank        = %u\n", desc->weight_bank);
+	dla_debug("batch_stride       = %u\n", desc->batch_stride);
+	dla_debug("post_extension     = %u\n", desc->post_extension);
+	dla_debug("pixel_override     = %u\n", desc->pixel_override);
+	dla_debug("release            = %u\n", desc->release);
+	dla_debug("input_width_csc    = %u\n", desc->input_width_csc);
+	dla_debug("input_height_csc   = %u\n", desc->input_height_csc);
+	dla_debug("input_channel_csc  = %u\n", desc->input_channel_csc);
+	dla_debug("kernel_width_csc   = %u\n", desc->kernel_width_csc);
+	dla_debug("kernel_height_csc  = %u\n", desc->kernel_height_csc);
+	dla_debug("kernel_channel_csc = %u\n", desc->kernel_channel_csc);
+	dla_debug("input_width_cmac   = %u\n", desc->input_width_cmac);
+	dla_debug("input_height_cmac  = %u\n", desc->input_height_cmac);
+	dla_debug("bytes_per_kernel   = %u\n", desc->bytes_per_kernel);
+	dla_debug("mean_ry            = %d\n", desc->mean_ry);
+	dla_debug("mean_gu            = %d\n", desc->mean_gu);
+	dla_debug("mean_bv            = %d\n", desc->mean_bv);
+	dla_debug("mean_ax            = %d\n", desc->mean_ax);
+	dla_debug("mean_format        = %u\n", desc->mean_format);
+	dla_debug("conv_stride_x      = %u\n", desc->conv_stride_x);
+	dla_debug("conv_stride_y      = %u\n", desc->conv_stride_y);
+	dla_debug("pad_x_left         = %u\n", desc->pad_x_left);
+	dla_debug("pad_x_right        = %u\n", desc->pad_x_right);
+	dla_debug("pad_y_top          = %u\n", desc->pad_y_top);
+	dla_debug("pad_y_bottom       = %u\n", desc->pad_y_bottom);
+	dla_debug("dilation_x         = %u\n", desc->dilation_x);
+	dla_debug("dilation_y         = %u\n", desc->dilation_y);
+	dla_debug("pra_truncate       = %u\n", desc->pra_truncate);
+	dla_debug("in_precision       = %u\n", desc->in_precision);
+	dla_debug("out_precision      = %u\n", desc->out_precision);
+	dla_debug("pad_val            = %d\n", desc->pad_val);
+	dla_debug("in_cvt             =\n");
+	dla_debug_converter(&desc->in_cvt);
+	dla_debug("out_cvt            =\n");
+	dla_debug_converter(&desc->out_cvt);
+}
+
+void
+dla_debug_conv_stats(struct dla_conv_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_conv_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("data_read_stall      = %u\n", stat->data_read_stall);
+	dla_debug("weight_read_stall    = %u\n", stat->weight_read_stall);
+	dla_debug("data_read_latency    = %u\n", stat->data_read_latency);
+	dla_debug("weight_read_latency  = %u\n", stat->weight_read_latency);
+	dla_debug("saturation_count     = %u\n", stat->saturation_count);
+	dla_debug("nan_data_num         = %u\n", stat->nan_data_num);
+	dla_debug("nan_weight_num       = %u\n", stat->nan_weight_num);
+	dla_debug("inf_data_num         = %u\n", stat->inf_data_num);
+	dla_debug("inf_weight_num       = %u\n", stat->inf_weight_num);
+	dla_debug("runtime              = %u\n", stat->runtime);
+}
+
+void
+dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_pdp_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi)
+{
+	int32_t i;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_pdp_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("precision               = %u\n", desc->precision);
+	dla_debug("padding_value           = [\n");
+	for (i = 0; i < PDP_PAD_VAL_NUM; i++)
+		dla_debug(" %d\n", desc->padding_value[i]);
+	dla_debug("]\n");
+	dla_debug("split_num               = %u\n", desc->split_num);
+	dla_debug("partial_in_width_first  = %u\n",
+					desc->partial_in_width_first);
+	dla_debug("partial_in_width_mid    = %u\n", desc->partial_in_width_mid);
+	dla_debug("partial_in_width_last   = %u\n", desc->partial_in_width_last);
+	dla_debug("partial_width_first     = %u\n", desc->partial_width_first);
+	dla_debug("partial_width_mid       = %u\n", desc->partial_width_mid);
+	dla_debug("partial_width_last      = %u\n", desc->partial_width_last);
+	dla_debug("pool_mode               = %u\n", desc->pool_mode);
+	dla_debug("pool_width              = %u\n", desc->pool_width);
+	dla_debug("pool_height             = %u\n", desc->pool_height);
+	dla_debug("stride_x                = %u\n", desc->stride_x);
+	dla_debug("stride_y                = %u\n", desc->stride_y);
+	dla_debug("pad_left                = %u\n", desc->pad_left);
+	dla_debug("pad_right               = %u\n", desc->pad_right);
+	dla_debug("pad_top                 = %u\n", desc->pad_top);
+	dla_debug("pad_bottom              = %u\n", desc->pad_bottom);
+}
+
+void
+dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_pdp_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("inf_input_num   = %u\n", stat->inf_input_num);
+	dla_debug("nan_input_num   = %u\n", stat->nan_input_num);
+	dla_debug("nan_output_num  = %u\n", stat->nan_output_num);
+	dla_debug("write_stall     = %u\n", stat->write_stall);
+	dla_debug("runtime         = %u\n", stat->runtime);
+}
+
+void
+dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_cdp_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_cdp_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("in_precision      = %u\n", desc->in_precision);
+	dla_debug("out_precision     = %u\n", desc->out_precision);
+	dla_debug("lut_index         = %d\n", desc->lut_index);
+	dla_debug("in_cvt             =\n");
+	dla_debug_converter(&desc->in_cvt);
+	dla_debug("out_cvt             =\n");
+	dla_debug_converter(&desc->out_cvt);
+	dla_debug("local_size        = %u\n", desc->local_size);
+	dla_debug("bypass_sqsum      = %u\n", desc->bypass_sqsum);
+	dla_debug("bypass_out_mul    = %u\n", desc->bypass_out_mul);
+}
+
+void
+dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_cdp_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("nan_input_num     = %u\n", stat->nan_input_num);
+	dla_debug("inf_input_num     = %u\n", stat->inf_input_num);
+	dla_debug("nan_output_num    = %u\n", stat->nan_output_num);
+	dla_debug("write_stall       = %u\n", stat->write_stall);
+	dla_debug("lut_uflow         = %u\n", stat->lut_uflow);
+	dla_debug("lut_oflow         = %u\n", stat->lut_oflow);
+	dla_debug("lut_hybrid        = %u\n", stat->lut_hybrid);
+	dla_debug("lut_le_hit        = %u\n", stat->lut_le_hit);
+	dla_debug("lut_lo_hit        = %u\n", stat->lut_lo_hit);
+	dla_debug("saturation_count  = %u\n", stat->saturation_count);
+	dla_debug("runtime           = %u\n", stat->runtime);
+}
+
+void
+dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_rubik_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_rubik_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("mode       = %u\n", desc->mode);
+	dla_debug("precision  = %u\n", desc->precision);
+	dla_debug("stride_x   = %u\n", desc->stride_x);
+	dla_debug("stride_y   = %u\n", desc->stride_y);
+}
+
+void
+dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_rubik_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("read_stall   = %u\n", stat->read_stall);
+	dla_debug("write_stall  = %u\n", stat->write_stall);
+	dla_debug("runtime      = %u\n", stat->runtime);
+}
+
+static void
+dla_debug_sdp_op(struct dla_sdp_op *sdp_op)
+{
+	dla_debug("    enable         = %u\n", sdp_op->enable);
+	dla_debug("    alu_type       = %u\n", sdp_op->alu_type);
+	dla_debug("    type           = %u\n", sdp_op->type);
+	dla_debug("    mode           = %u\n", sdp_op->mode);
+	dla_debug("    act            = %u\n", sdp_op->act);
+	dla_debug("    shift_value    = %u\n", sdp_op->shift_value);
+	dla_debug("    truncate       = %u\n", sdp_op->truncate);
+	dla_debug("    precision      = %u\n", sdp_op->precision);
+	dla_debug("    alu_operand    = %d\n", sdp_op->alu_operand);
+	dla_debug("    mul_operand    = %d\n", sdp_op->mul_operand);
+	dla_debug("cvt.alu_cvt          =\n");
+	dla_debug_converter(&sdp_op->cvt.alu_cvt);
+	dla_debug("cvt.mul_cvt          =\n");
+	dla_debug_converter(&sdp_op->cvt.mul_cvt);
+	dla_debug("]\n");
+}
+
+void
+dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_sdp_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("x1_data             = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->x1_data);
+	dla_debug("x2_data             = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->x2_data);
+	dla_debug("y_data              = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->y_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_sdp_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_precision    = %u\n", desc->src_precision);
+	dla_debug("dst_precision    = %u\n", desc->dst_precision);
+	dla_debug("lut_index        = %d\n", desc->lut_index);
+	dla_debug("out_cvt          =\n");
+	dla_debug_converter(&desc->out_cvt);
+	dla_debug("conv_mode        = %u\n", desc->conv_mode);
+	dla_debug("batch_num        = %u\n", desc->batch_num);
+	dla_debug("batch_stride     = %u\n", desc->batch_stride);
+	dla_debug("x1_op            = [ dla_sdp_op =>\n");
+	dla_debug_sdp_op(&desc->x1_op);
+	dla_debug("x2_op            = [ dla_sdp_op =>\n");
+	dla_debug_sdp_op(&desc->x2_op);
+	dla_debug("y_op             = [ dla_sdp_op =>\n");
+	dla_debug_sdp_op(&desc->y_op);
+}
+
+void
+dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_sdp_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("nan_input_num     = %u\n", stat->nan_input_num);
+	dla_debug("inf_input_num     = %u\n", stat->inf_input_num);
+	dla_debug("nan_output_num    = %u\n", stat->nan_output_num);
+	dla_debug("wdma_write_stall  = %u\n", stat->wdma_write_stall);
+	dla_debug("lut_underflow     = %u\n", stat->lut_underflow);
+	dla_debug("lut_overflow      = %u\n", stat->lut_overflow);
+	dla_debug("lut_hybrid        = %u\n", stat->lut_hybrid);
+	dla_debug("lut_le_hit        = %u\n", stat->lut_le_hit);
+	dla_debug("lut_lo_hit        = %u\n", stat->lut_lo_hit);
+	dla_debug("saturation_count  = %u\n", stat->saturation_count);
+	dla_debug("runtime           = %u\n", stat->runtime);
+}
+#endif /* DEBUG_NETWORK_DATA */
diff --git a/drivers/nvdla/engine_debug.h b/drivers/nvdla/engine_debug.h
new file mode 100644
index 000000000000..d953fc4c2a91
--- /dev/null
+++ b/drivers/nvdla/engine_debug.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_ENGINE_DEBUG_H_
+#define __FIRMWARE_ENGINE_DEBUG_H_
+
+#include <dla_debug.h>
+#include <dla_interface.h>
+
+#if DEBUG_NETWORK_DATA
+void
+dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi);
+void
+dla_debug_network_desc(struct dla_network_desc *network_desc);
+void
+dla_debug_address_info(struct dla_task *task);
+void
+dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi);
+void
+dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi);
+void
+dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat);
+void
+dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi);
+void
+dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi);
+void
+dla_debug_conv_stats(struct dla_conv_stat_desc *stat);
+void
+dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi);
+void
+dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi);
+void
+dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat);
+void
+dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi);
+void
+dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi);
+void
+dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat);
+void
+dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi);
+void
+dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi);
+void
+dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat);
+void
+dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi);
+void
+dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi);
+void
+dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat);
+void
+dla_debug_lut_params(struct dla_lut_param *lut_param);
+
+#else
+
+static inline void
+dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_network_desc(struct dla_network_desc *network_desc) {}
+static inline void
+dla_debug_address_info(struct dla_task *task) {}
+static inline void
+dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat) {}
+static inline void
+dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_conv_stats(struct dla_conv_stat_desc *stat) {}
+static inline void
+dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat) {}
+static inline void
+dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat) {}
+static inline void
+dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat) {}
+static inline void
+dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat) {}
+static inline void
+dla_debug_lut_params(struct dla_lut_param *lut_param) {}
+
+#endif /* DEBUG_NETWORK_DATA */
+#endif /* __FIRMWARE_ENGINE_DEBUG_H_ */
diff --git a/drivers/nvdla/engine_isr.c b/drivers/nvdla/engine_isr.c
new file mode 100644
index 000000000000..ae9dbddf6026
--- /dev/null
+++ b/drivers/nvdla/engine_isr.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_engine.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+
+int32_t dla_isr_handler(void *engine_data)
+{
+	uint32_t mask;
+	uint32_t reg;
+	struct dla_processor *processor = NULL;
+	struct dla_processor_group *group;
+	struct dla_engine *engine = (struct dla_engine *)engine_data;
+
+	mask = glb_reg_read(S_INTR_MASK);
+	reg = glb_reg_read(S_INTR_STATUS);
+
+	dla_trace("Enter: dla_isr_handler, reg:%x, mask:%x\n", reg, mask);
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CACC_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CACC_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, SDP_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_SDP];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, SDP_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_SDP];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDP_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CDP];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDP_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CDP];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, RUBIK_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_RUBIK];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, RUBIK_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_RUBIK];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, PDP_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_PDP];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, PDP_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_PDP];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, BDMA_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_BDMA];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, BDMA_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_BDMA];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_DAT_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_CDMA_DT_DONE);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_DAT_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_CDMA_DT_DONE);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_WT_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_CDMA_WT_DONE);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_WT_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_CDMA_WT_DONE);
+	}
+
+	glb_reg_write(S_INTR_STATUS, reg);
+
+	mask = glb_reg_read(S_INTR_MASK);
+	reg = glb_reg_read(S_INTR_STATUS);
+
+	dla_trace("Exit: dla_isr_handler, reg:%x, mask:%x\n", reg, mask);
+	RETURN(0);
+}
diff --git a/drivers/nvdla/include/dla_debug.h b/drivers/nvdla/include/dla_debug.h
new file mode 100644
index 000000000000..bef99d620789
--- /dev/null
+++ b/drivers/nvdla/include/dla_debug.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_DEBUG_H_
+#define __FIRMWARE_DLA_DEBUG_H_
+
+#define STRINGIFY(s) #s
+#define DEFER_STRINGIFY(s) STRINGIFY(s)
+#define FILELINE DEFER_STRINGIFY(__LINE__)
+#define FILENAME DEFER_STRINGIFY(__FILE__)
+
+#define LOG_EVENT_BDMA_SHIFT		0U
+#define LOG_EVENT_CONV_SHIFT		4U
+#define LOG_EVENT_SDP_SHIFT		8U
+#define LOG_EVENT_PDP_SHIFT		12U
+#define LOG_EVENT_CDP_SHIFT		16U
+#define LOG_EVENT_RBK_SHIFT		20U
+#define LOG_EVENT_GROUP_SHIFT		24U
+#define LOG_EVENT_ROI_SHIFT		28U
+
+#define LOG_TASK_START			1
+#define LOG_TASK_END			2
+#define LOG_READ_OP_CONFIG_START	3
+#define LOG_READ_OP_CONFIG_END		4
+#define LOG_READ_SURF_CONFIG_START	5
+#define LOG_READ_SURF_CONFIG_END	6
+#define LOG_PROGRAM_START		7
+#define LOG_PROGRAM_END			8
+#define LOG_OPERATION_START		9
+#define LOG_OPERATION_END		10
+
+#define LOG_EVENT(roi, group, processor, event)
+
+/**
+ * Used to enable/disable reading stat registers
+ */
+#define STAT_ENABLE		1
+
+/**
+ * Used to print debug network data
+ */
+#define DEBUG_NETWORK_DATA		0
+
+#define pr_dump_stack(format, ...)
+#define dla_trace(format, ...)
+
+#define assert(condition)
+
+#define RETURN(err) { return (err); }
+
+#define DEBUG_ASSERT
+
+#ifdef DEBUG_ASSERT
+#define ASSERT_GOTO(_condition, _ret, _err_value, _goto)	\
+do {								\
+	if (!(_condition)) {					\
+		dla_error("Assertion Fail(" FILENAME FILELINE "):" \
+					STRINGIFY(_condition));	\
+		_ret = _err_value;				\
+		goto _goto;					\
+	} else {						\
+		_ret = 0;					\
+	}							\
+} while (0)
+#else
+#define ASSERT_GOTO(_condition, _ret, _err_value, _goto) assert(condition)
+#endif /* DEBUG_ASSERT */
+
+#endif
diff --git a/drivers/nvdla/include/dla_engine.h b/drivers/nvdla/include/dla_engine.h
new file mode 100644
index 000000000000..707adc41d5d4
--- /dev/null
+++ b/drivers/nvdla/include/dla_engine.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DLA_ENGINE_H_
+#define __DLA_ENGINE_H_
+
+#include <dla_interface.h>
+#include <dla_sched.h>
+
+struct dla_processor_group {
+	uint8_t id;
+	uint8_t rdma_id;
+	uint8_t active;
+	uint8_t events;
+	uint8_t roi_index;
+	uint8_t is_rdma_needed;
+	uint8_t pending;
+	int32_t lut_index;
+	uint8_t programming;
+	uint64_t start_time;
+
+	struct dla_common_op_desc *op_desc;
+	struct dla_common_op_desc *consumers[DLA_OP_NUM];
+	struct dla_common_op_desc *fused_parent;
+	union dla_operation_container *operation_desc;
+	union dla_surface_container *surface_desc;
+};
+
+struct dla_processor {
+	const char *name;
+	uint8_t op_type;
+	uint8_t consumer_ptr;
+	uint8_t roi_index;
+	uint8_t group_status;
+	uint8_t rdma_status;
+	uint8_t last_group;
+
+	struct dla_common_op_desc *tail_op;
+	struct dla_processor_group groups[DLA_NUM_GROUPS];
+	union dla_stat_container *stat_data_desc;
+
+	int32_t (*is_ready)(struct dla_processor *processor,
+				  struct dla_processor_group *group);
+	int32_t (*enable)(struct dla_processor_group *group);
+	int32_t (*program)(struct dla_processor_group *group);
+	void (*set_producer)(int32_t group_id, int32_t rdma_id);
+	void (*dump_config)(struct dla_processor_group *group);
+	void (*rdma_check)(struct dla_processor_group *group);
+	void (*get_stat_data)(struct dla_processor *processor,
+				struct dla_processor_group *group);
+	void (*dump_stat)(struct dla_processor *processor);
+};
+
+struct dla_engine {
+	struct dla_task *task;
+	struct dla_config *config_data;
+	struct dla_network_desc *network;
+	struct dla_processor processors[DLA_OP_NUM];
+
+	uint16_t num_proc_hwl;
+	int32_t status;
+	uint32_t stat_enable;
+
+	void *driver_context;
+};
+
+struct dla_engine *dla_get_engine(void);
+
+#endif
diff --git a/drivers/nvdla/include/dla_err.h b/drivers/nvdla/include/dla_err.h
new file mode 100644
index 000000000000..d9efcd08d8f7
--- /dev/null
+++ b/drivers/nvdla/include/dla_err.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_ERR_H_
+#define __FIRMWARE_DLA_ERR_H_
+
+#define ERR(code) -DLA_ERR_##code
+
+#define DLA_ERR_NONE			0
+#define DLA_ERR_INVALID_METHOD		1
+#define DLA_ERR_INVALID_TASK		2
+#define DLA_ERR_INVALID_INPUT		3
+#define DLA_ERR_INVALID_FALC_DMA	4
+#define DLA_ERR_INVALID_QUEUE		5
+#define DLA_ERR_INVALID_PREACTION	6
+#define DLA_ERR_INVALID_POSTACTION	7
+#define DLA_ERR_NO_MEM			8
+#define DLA_ERR_INVALID_DESC_VER	9
+#define DLA_ERR_INVALID_ENGINE_ID	10
+#define DLA_ERR_INVALID_REGION		11
+#define DLA_ERR_PROCESSOR_BUSY		12
+#define DLA_ERR_RETRY			13
+#define DLA_ERR_TASK_STATUS_MISMATCH	14
+
+#endif
diff --git a/drivers/nvdla/include/dla_interface.h b/drivers/nvdla/include/dla_interface.h
new file mode 100644
index 000000000000..cbf4791bd909
--- /dev/null
+++ b/drivers/nvdla/include/dla_interface.h
@@ -0,0 +1,886 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_INTERFACE_H_
+#define __FIRMWARE_DLA_INTERFACE_H_
+
+#include <nvdla_interface.h>
+
+/**
+ * @ingroup Processors
+ * @name DLA Processors
+ * Processor modules in DLA engine. Each processor has it's
+ * own operation a.k.a. HW layer. Network is formed using
+ * graph of these operations
+ * @{
+ */
+#define DLA_OP_BDMA		0
+#define DLA_OP_CONV		1
+#define DLA_OP_SDP		2
+#define DLA_OP_PDP		3
+#define DLA_OP_CDP		4
+#define DLA_OP_RUBIK		5
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Maximum number of processors
+ * @brief DLA ash 6 processors
+ * @{
+ */
+#define DLA_OP_NUM		6
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Number of groups
+ * @brief Each processor has 2 groups of registers
+ * @{
+ */
+#define DLA_NUM_GROUPS		2
+/** @} */
+
+/**
+ * Network descriptor
+ *
+ * Contains all information to execute a network
+ *
+ * @op_head: Index of first operation of each type in operations list
+ * @num_rois: Number of ROIs
+ * @num_operations: Number of operations in one list
+ * @num_luts: Number of LUTs
+ */
+struct dla_network_desc {
+	int16_t operation_desc_index;
+	int16_t surface_desc_index;
+
+	int16_t dependency_graph_index;
+	int16_t lut_data_index;
+
+	int16_t roi_array_index;
+	int16_t surface_index;
+
+	int16_t stat_list_index;
+	int16_t reserved1;
+
+	int16_t op_head[DLA_OP_NUM];
+
+	uint16_t num_rois;
+	uint16_t num_operations;
+
+	uint16_t num_luts;
+	uint16_t num_addresses;
+
+	int16_t input_layer;
+	uint8_t dynamic_roi;
+	uint8_t reserved0;
+} __packed __aligned(4);
+
+/**
+ * @name Memory types
+ * @brief DLA engnine can read/write to/from 3 memory types
+ * @{
+ */
+#define DLA_MEM_MC			0 /* External DRAM */
+#define DLA_MEM_CV			1 /* CV-SRAM */
+#define DLA_MEM_HW			2 /* DLA sub-module */
+/** @} */
+
+/**
+ * @ingroup Events
+ * @name Operation events
+ * @brief Different events triggered by an operations
+ * @{
+ */
+#define DLA_EVENT_OP_COMPLETED		1
+#define DLA_EVENT_OP_PROGRAMMED		2
+#define DLA_EVENT_OP_ENABLED		3
+#define DLA_EVENT_CDMA_WT_DONE		4
+#define DLA_EVENT_CDMA_DT_DONE		5
+/** @} */
+
+struct dla_consumer {
+	int16_t index; /* the index of dla_common_op_desc in dep_graph_addr */
+	uint8_t event;
+	uint8_t res;
+} __packed __aligned(4);
+
+struct dla_common_op_desc {
+	int16_t index; /* set by ucode */
+	int8_t roi_index;
+	uint8_t op_type;
+
+	uint8_t dependency_count;
+	uint8_t reserved0[3];
+
+	struct dla_consumer consumers[DLA_OP_NUM];
+	struct dla_consumer fused_parent;
+} __packed __aligned(4);
+
+struct dla_roi_array_desc {
+	uint32_t array_length;
+
+	uint32_t array_reserved;
+} __packed __aligned(4);
+
+struct dla_roi_desc {
+	uint32_t left;
+
+	uint32_t top;
+
+	uint32_t right;
+
+	uint32_t bottom;
+} __packed __aligned(4);
+
+/**
+ * @ingroup BDMA
+ * @name Maximum BDMA transfers
+ * @brief BDMA supports multiple transfers in operation. This indicates
+ *        maximum number of transfers possible in one operation.
+ * @{
+ */
+#define NUM_MAX_BDMA_OPS	20
+/** @} */
+
+struct dla_bdma_transfer_desc {
+	int16_t source_address;
+	int16_t destination_address;
+
+	uint32_t line_size;
+
+	uint32_t line_repeat;
+
+	uint32_t source_line;
+
+	uint32_t destination_line;
+
+	uint32_t surface_repeat;
+
+	uint32_t source_surface;
+
+	uint32_t destination_surface;
+} __packed __aligned(4);
+
+struct dla_bdma_surface_desc {
+	uint8_t source_type;
+	uint8_t destination_type;
+	uint16_t num_transfers;
+
+	struct dla_bdma_transfer_desc transfers[NUM_MAX_BDMA_OPS];
+} __packed __aligned(4);
+
+struct dla_bdma_op_desc {
+	uint16_t num_transfers;
+	uint16_t reserved0;
+} __packed __aligned(4);
+
+struct dla_bdma_stat_desc {
+	uint32_t read_stall;
+	uint32_t write_stall;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+/**
+ * @ingroup Convolution
+ * @name Convolution mode
+ * @brief Convolution modes support by DLA
+ * @{
+ */
+#define CONV_MODE_DIRECT	0
+#define CONV_MODE_WINOGRAD	1
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Precision BPE mapping
+ * @brief Precision formats and Bit Per Elements mapping
+ * @{
+ */
+#define BPE_PRECISION_INT8		1
+#define BPE_PRECISION_INT16		2
+#define BPE_PRECISION_FP16		2
+/** @} */
+
+
+/**
+ * @ingroup Processors
+ * @name Precision types
+ * @brief Precision formats supported by DLA engine
+ * @{
+ */
+#define PRECISION_INT8		0
+#define PRECISION_INT16		1
+#define PRECISION_FP16		2
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Data formats
+ * @brief Data formats supported by DLA engine
+ * @{
+ */
+#define FORMAT_T_R8			0
+#define FORMAT_T_R10			1
+#define FORMAT_T_R12			2
+#define FORMAT_T_R16			3
+#define FORMAT_T_R16_I			4
+#define FORMAT_T_R16_F			5
+#define FORMAT_T_A16B16G16R16		6
+#define FORMAT_T_X16B16G16R16		7
+#define FORMAT_T_A16B16G16R16_F		8
+#define FORMAT_T_A16Y16U16V16		9
+#define FORMAT_T_V16U16Y16A16		10
+#define FORMAT_T_A16Y16U16V16_F		11
+#define FORMAT_T_A8B8G8R8		12
+#define FORMAT_T_A8R8G8B8		13
+#define FORMAT_T_B8G8R8A8		14
+#define FORMAT_T_R8G8B8A8		15
+#define FORMAT_T_X8B8G8R8		16
+#define FORMAT_T_X8R8G8B8		17
+#define FORMAT_T_B8G8R8X8		18
+#define FORMAT_T_R8G8B8X8		19
+#define FORMAT_T_A2B10G10R10		20
+#define FORMAT_T_A2R10G10B10		21
+#define FORMAT_T_B10G10R10A2		22
+#define FORMAT_T_R10G10B10A2		23
+#define FORMAT_T_A2Y10U10V10		24
+#define FORMAT_T_V10U10Y10A2		25
+#define FORMAT_T_A8Y8U8V8			26
+#define FORMAT_T_V8U8Y8A8			27
+#define FORMAT_T_Y8___U8V8_N444		28
+#define FORMAT_T_Y8___V8U8_N444		29
+#define FORMAT_T_Y10___U10V10_N444	30
+#define FORMAT_T_Y10___V10U10_N444	31
+#define FORMAT_T_Y12___U12V12_N444	32
+#define FORMAT_T_Y12___V12U12_N444	33
+#define FORMAT_T_Y16___U16V16_N444	34
+#define FORMAT_T_Y16___V16U16_N444	35
+#define FORMAT_FEATURE			36
+/** @} */
+
+/**
+ * @ingroup Convolution
+ * @name Pixel mapping
+ * @brief Pixel mapping formats supported for image input in Convolution
+ * @{
+ */
+#define MAP_PITCH_LINEAR		0
+/** @} */
+
+/**
+ * @ingroup Convolution
+ * @name Weight formats
+ * @brief Weight data formats supported in Convolution
+ * @{
+ */
+#define WEIGHT_FORMAT_UNCOMPRESSED	0
+#define WEIGHT_FORMAT_COMPRESSED	1
+/** @} */
+
+/**
+ * @ingroup Convolution
+ * @name Mean data format
+ * @brief Mean data formats supported in Convolution
+ * @{
+ */
+#define MEAN_FORMAT_DISABLE     0
+#define MEAN_FORMAT_ENABLE      1
+/** @} */
+
+struct dla_cvt_param {
+	int16_t  scale;
+	uint8_t  truncate;
+	uint8_t  enable;
+
+	int32_t  offset;
+} __packed __aligned(4);
+
+struct dla_data_cube {
+	uint16_t type; /* dla_mem_type */
+	int16_t address; /* offset to the actual IOVA in task.address_list */
+
+	uint32_t offset; /* offset within address */
+	uint32_t size;
+
+	/* cube dimensions */
+	uint16_t width;
+	uint16_t height;
+
+	uint16_t channel;
+	uint16_t reserved0;
+
+	/* stride information */
+	uint32_t line_stride;
+	uint32_t surf_stride;
+
+	/* For Rubik only */
+	uint32_t plane_stride;
+} __packed __aligned(4);
+
+#define PIXEL_OVERRIDE_UINT 0
+#define PIXEL_OVERRIDE_INT  1
+
+struct dla_conv_surface_desc {
+	/* Data cube */
+	struct dla_data_cube weight_data;
+	struct dla_data_cube wmb_data;
+	struct dla_data_cube wgs_data;
+	struct dla_data_cube src_data;
+	struct dla_data_cube dst_data;
+
+	/**
+	 * u_addr = input_data.source_addr + offset_u
+	 * this field should be set when YUV is not interleave format
+	 *
+	 */
+	int64_t offset_u;
+
+	/* line stride for 2nd plane, must be 32bytes aligned */
+	uint32_t in_line_uv_stride;
+} __packed __aligned(4);
+
+struct dla_conv_op_desc {
+	/* Performance parameters */
+
+	/* dla_conv_mode */
+	uint8_t conv_mode;
+	uint8_t data_reuse;
+	uint8_t weight_reuse;
+	uint8_t skip_data_rls;
+
+	uint8_t skip_weight_rls;
+	uint8_t reserved0;
+	uint16_t entry_per_slice;
+
+	/* dla_data_format */
+	uint8_t data_format;
+	/* dla_pixel_mapping */
+	uint8_t pixel_mapping;
+	/* number of free slices before fetch */
+	uint16_t fetch_grain;
+
+	uint8_t reserved_b[8];
+
+	/* batch_num */
+	uint8_t batch;
+	/* dla_weight_format */
+	uint8_t weight_format;
+	uint8_t data_bank;
+	uint8_t weight_bank;
+
+	/* the offset in bytes of each data cube in a batch */
+	uint32_t batch_stride;
+
+	uint8_t post_extension;
+	uint8_t pixel_override;
+	/* number of slices need to be released */
+	uint16_t release;
+
+	 /* The input cube dimension for CSC */
+	uint16_t input_width_csc;
+	uint16_t input_height_csc;
+
+	uint16_t input_channel_csc;
+	uint16_t kernel_width_csc;
+
+	uint16_t kernel_height_csc;
+	uint16_t kernel_channel_csc;
+
+	/* The input cube dimension for CMAC */
+	uint16_t input_width_cmac;
+	uint16_t input_height_cmac;
+
+	/* actual size in bytes */
+	uint32_t bytes_per_kernel;
+
+	/* Algorithm parameters */
+
+	int16_t mean_ry; /* mean value for red in RGB or Y in YUV */
+	int16_t mean_gu; /* mean value for green in RGB or U in YUV */
+
+	int16_t mean_bv; /* mean value for blue in RGB or V in YUV */
+	int16_t mean_ax;
+
+	uint8_t mean_format; /* dla_mean_format */
+	uint8_t conv_stride_x;
+	uint8_t conv_stride_y;
+	uint8_t pad_x_left;
+
+	uint8_t pad_x_right;
+	uint8_t pad_y_top;
+	uint8_t pad_y_bottom;
+	uint8_t dilation_x;
+
+	uint8_t dilation_y;
+	uint8_t reserved2[2];
+
+	/* Precision parameters */
+	uint8_t pra_truncate;
+
+	uint8_t in_precision;
+	/* The output precision from CONV, it's the MAC processing precison */
+	uint8_t out_precision;
+	int16_t pad_val;
+
+	/* input converter parameters */
+	struct dla_cvt_param in_cvt;
+	/* output converter parameters, support truncate only */
+	struct dla_cvt_param out_cvt;
+
+} __packed __aligned(4);
+
+struct dla_conv_stat_desc {
+	uint32_t data_read_stall;
+	uint32_t weight_read_stall;
+	uint32_t data_read_latency;
+	uint32_t weight_read_latency;
+	uint32_t saturation_count;
+	uint32_t nan_data_num;
+	uint32_t nan_weight_num;
+	uint32_t inf_data_num;
+	uint32_t inf_weight_num;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+/**
+ * @ingroup SDP
+ * @name Activation functions
+ * @brief Activation functions supported in SDP
+ * @{
+ */
+#define ACTIVATION_NONE		0
+#define ACTIVATION_RELU		1
+#define ACTIVATION_LUT		2
+#define ACTIVATION_PRELU	3
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT size
+ * @brief LUT sizes for linear and exponentila LUT
+ * @{
+ */
+#define LUT_LINEAR_EXP_TABLE_ENTRY_LOG2		6
+#define LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2	8
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT types
+ * @brief DLA supports two types of LUT, linear and exonential
+ * @{
+ */
+#define LUT_LINEAR_EXP_TABLE		0
+#define LUT_LINEAR_ONLY_TABLE		1
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT methods
+ * @brief DLA supports two types of LUT, linear and exonential
+ * @{
+ */
+#define LUT_METHOD_EXPONENTIAL		0
+#define LUT_METHOD_LINEAR		1
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT
+ * @brief DLA supports two types of LUT, linear and exonential
+ * @{
+ */
+#define LUT_PRI_LINEAR_EXP		0
+#define LUT_PRI_LINEAR_ONLY		1
+/** @} */
+
+union dla_lut_offset {
+	/**
+	 * Number should be substracted on log domain before look up
+	 * exponetial table it has the same definition as hardware
+	 * thus input scaling should also take into account when
+	 * set this field.
+	 */
+	int8_t exp_offset;
+	/**
+	 * Number of bits should be right shift before looking
+	 * up linear table
+	 */
+	int8_t frac_bits;
+	uint16_t reserved0;
+};
+
+/**
+ * This struct is used to represent floating point values by INT
+ * suppose we have a float point number fp_x, it will be represented
+ * as:
+ *
+ * fp_x = scale_int_x>>(shifter_x)
+ *
+ * This is very useful for INT pipeline;
+ */
+struct dla_float_data {
+	int16_t scale;
+	int8_t shifter;
+	uint8_t reserved0;
+} __packed __aligned(4);
+
+/**
+ * For INT pipeline, we use the struct above to represent a floating number;
+ * For FP16 pipeline, we should store the FP16 encoded value into a uint16_t
+ * container
+ */
+union dla_slope {
+	struct dla_float_data data_i;
+
+	uint16_t data_f;
+};
+
+struct dla_lut_param {
+	/**
+	 * value of expression ((1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1) is 65,
+	 * ((1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1) is 257, and int16_t is of
+	 * 2Byte. And below two statement's combined memory size is 644 Byte.
+	 *
+	 * NOTE: below two declaration combined size should always be multiple
+	 * of 4.
+	 */
+	int16_t linear_exp_table[(1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1];
+	int16_t linear_only_table[(1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1];
+
+	union dla_lut_offset linear_exp_offset;
+	union dla_lut_offset linear_only_offset;
+
+	/**
+	 * The start and end point of raw table,
+	 * valid when raw_method=LINEAR only
+	 */
+	uint64_t linear_exp_start;
+	uint64_t linear_exp_end;
+	uint64_t linear_only_start;
+	uint64_t linear_only_end;
+
+	union dla_slope linear_exp_underflow_slope;
+	union dla_slope linear_exp_overflow_slope;
+	union dla_slope linear_only_underflow_slope;
+	union dla_slope linear_only_overflow_slope;
+
+	/**
+	 * dla_lut_priority, when both lut are hit(or one overflow,
+	 * the other underflow), which one should be selected as output
+	 */
+	uint8_t hybrid_priority;
+	uint8_t underflow_priority;
+	uint8_t overflow_priority;
+	uint8_t method; /* dla_lut_method */
+} __packed __aligned(4);
+
+struct dla_sdp_surface_desc {
+	/* Data cube */
+	/* source input cube, available when SDP working on offline mode */
+	struct dla_data_cube src_data;
+
+	/* X1 input cube */
+	struct dla_data_cube x1_data;
+
+	/* X2 input cube */
+	struct dla_data_cube x2_data;
+
+	/* Y input cube */
+	struct dla_data_cube y_data;
+
+	/* Output cube */
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+#define SDP_OP_NONE		0
+#define SDP_OP_MUL		1
+#define SDP_OP_ADD		2
+#define SDP_OP_BOTH		3
+
+#define SDP_ALU_OP_MAX		0
+#define SDP_ALU_OP_MIN		1
+#define SDP_ALU_OP_SUM		2
+#define SDP_ALU_OP_EQL		3
+
+#define SDP_OP_PER_LAYER	0
+#define SDP_OP_PER_KERNEL	1
+#define SDP_OP_PER_POINT	2
+
+struct dla_sdp_cvt {
+	struct dla_cvt_param alu_cvt;
+	struct dla_cvt_param mul_cvt;
+} __packed __aligned(4);
+
+struct dla_sdp_op {
+	uint8_t enable;
+	uint8_t alu_type; /* dla_sdp_alu_op_type */
+	uint8_t type; /* dla_sdp_op_type */
+	uint8_t mode; /* dla_sdp_op_mode */
+
+	uint8_t act; /* dla_act_type */
+	uint8_t shift_value; /* left shift */
+	uint8_t truncate;
+	uint8_t precision;
+
+	int32_t alu_operand;
+	int32_t mul_operand;
+
+	struct dla_sdp_cvt  cvt;
+} __packed __aligned(4);
+
+struct dla_sdp_op_desc {
+	/* Precision parameters */
+	/* dla_precision */
+	uint8_t src_precision;
+	uint8_t dst_precision;
+	int16_t lut_index;
+
+	struct dla_cvt_param out_cvt;
+
+	/* Performance parameters */
+	/* dla_conv_mode */
+	uint8_t conv_mode;
+	uint8_t batch_num;
+	uint16_t reserved0;
+
+	uint32_t batch_stride;	/* will be used when batch_num > 1 */
+
+	/* Algorithm parameters */
+	struct dla_sdp_op x1_op;
+	struct dla_sdp_op x2_op;
+	struct dla_sdp_op y_op;
+} __packed __aligned(4);
+
+struct dla_sdp_stat_desc {
+	uint32_t nan_input_num;
+	uint32_t inf_input_num;
+	uint32_t nan_output_num;
+	uint32_t wdma_write_stall;
+	uint32_t lut_underflow;
+	uint32_t lut_overflow;
+	uint32_t lut_hybrid;
+	uint32_t lut_le_hit;
+	uint32_t lut_lo_hit;
+	uint32_t saturation_count;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+#define POOL_MODE_AVG		0
+#define POOL_MODE_MAX		1
+#define POOL_MODE_MIN		2
+
+#define POOL_SIZE_1		0
+#define POOL_SIZE_2		1
+#define POOL_SIZE_3		2
+#define POOL_SIZE_4		3
+#define POOL_SIZE_5		4
+#define POOL_SIZE_6		5
+#define POOL_SIZE_7		6
+#define POOL_SIZE_8		7
+
+#define PDP_PAD_VAL_NUM	7
+
+struct dla_pdp_surface_desc {
+	/* Data cube */
+	struct dla_data_cube src_data;
+
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+struct dla_pdp_op_desc {
+	/* Performance parameters */
+	uint16_t  partial_in_width_first;
+	uint16_t  partial_in_width_mid;
+
+	uint16_t  partial_in_width_last;
+	uint16_t  partial_width_first;
+
+	uint16_t  partial_width_mid;
+	uint16_t  partial_width_last;
+
+	uint8_t   split_num;
+
+	/* Algorithm parameters */
+	uint8_t  pool_mode; /* dla_pool_mode */
+	uint8_t  pool_width; /* dla_pool_width */
+	uint8_t  pool_height; /* dla_pool_height */
+
+	uint8_t  stride_x;
+	uint8_t  stride_y;
+
+	/**
+	 * The left/right padding size,
+	 * pad_right might be less than pad_left
+	 */
+	uint8_t  pad_left;
+	uint8_t  pad_right;
+
+	/* The top/bottom padding size */
+	uint8_t  pad_top;
+	uint8_t  pad_bottom;
+
+	/* Precision parameters */
+	uint8_t  precision; /* dla_precision */
+	uint8_t  reserved0;
+	/**
+	 * if input has non-zero "offset", this value should be set
+	 * There'll be 7 different paddding values, the relationship between
+	 * those versions are:
+	 * padding_value[0] = -offset*scaling;
+	 * padding_value[1] = 2*padding_value[0]
+	 * padding_value[2] = 3*padding_value[0]
+	 * ...
+	 * The purpose is to avoid ucode implement FP16
+	 * multiplier(for FP16 mode)
+	 */
+	int32_t  padding_value[PDP_PAD_VAL_NUM];
+} __packed __aligned(4);
+
+struct dla_pdp_stat_desc {
+	uint32_t inf_input_num;
+	uint32_t nan_input_num;
+	uint32_t nan_output_num;
+	uint32_t write_stall;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+struct dla_cdp_surface_desc {
+	/* Data cube */
+	struct dla_data_cube src_data;
+
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+struct dla_cdp_op_desc {
+	/* Precision parameters */
+
+	/* dla_precision */
+	uint8_t  in_precision;
+	uint8_t  out_precision;
+	int16_t  lut_index;
+
+	struct dla_cvt_param in_cvt;
+	struct dla_cvt_param out_cvt;
+
+	/* Performance parameters */
+
+	/* Algorithm parameters */
+	uint8_t  local_size;
+	uint8_t  bypass_sqsum;
+	uint8_t  bypass_out_mul;
+	uint8_t  reserved0;
+} __packed __aligned(4);
+
+struct dla_cdp_stat_desc {
+	uint32_t nan_input_num;
+	uint32_t inf_input_num;
+	uint32_t nan_output_num;
+	uint32_t write_stall;
+	uint32_t lut_uflow;
+	uint32_t lut_oflow;
+	uint32_t lut_hybrid;
+	uint32_t lut_le_hit;
+	uint32_t lut_lo_hit;
+	uint32_t saturation_count;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+struct dla_rubik_surface_desc {
+	/* Data cube */
+	struct dla_data_cube src_data;
+
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+/* rubik mode */
+#define RUBIK_MODE_CONTRACT	0
+#define RUBIK_MODE_SPLIT	1
+#define RUBIK_MODE_MERGE	2
+
+struct dla_rubik_op_desc {
+	/* Precision parameters */
+	uint8_t mode;
+	uint8_t precision;
+	uint8_t stride_x;
+	uint8_t stride_y;
+} __packed __aligned(4);
+
+struct dla_rubik_stat_desc {
+	uint32_t read_stall;
+	uint32_t write_stall;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+union dla_surface_container {
+	struct dla_bdma_surface_desc bdma_surface;
+	struct dla_conv_surface_desc conv_surface;
+	struct dla_sdp_surface_desc sdp_surface;
+	struct dla_pdp_surface_desc pdp_surface;
+	struct dla_cdp_surface_desc cdp_surface;
+	struct dla_rubik_surface_desc rubik_surface;
+};
+
+union dla_operation_container {
+	struct dla_bdma_op_desc bdma_op;
+	struct dla_conv_op_desc conv_op;
+	struct dla_sdp_op_desc sdp_op;
+	struct dla_pdp_op_desc pdp_op;
+	struct dla_cdp_op_desc cdp_op;
+	struct dla_rubik_op_desc rubik_op;
+};
+
+union dla_stat_container {
+	struct dla_bdma_stat_desc bdma_stat;
+	struct dla_conv_stat_desc conv_stat;
+	struct dla_sdp_stat_desc sdp_stat;
+	struct dla_pdp_stat_desc pdp_stat;
+	struct dla_cdp_stat_desc cdp_stat;
+	struct dla_rubik_stat_desc rubik_stat;
+};
+
+/**
+ * status notifier structure
+ *
+ * @address: 64-bit timestamp representing the time at which
+ * the notifier was written
+ * @status_engine: status work captured from HW engine
+ * @subframe: NA
+ * @status_task: status word as configured from an action list
+ */
+struct dla_task_status {
+	uint64_t timestamp;
+
+	uint32_t status_engine;
+
+	uint16_t subframe;
+	uint16_t status_task;
+} __packed __aligned(4);
+
+#endif
diff --git a/drivers/nvdla/include/dla_sched.h b/drivers/nvdla/include/dla_sched.h
new file mode 100644
index 000000000000..7ed35487da16
--- /dev/null
+++ b/drivers/nvdla/include/dla_sched.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DLA_SCHED_H_
+#define __DLA_SCHED_H_
+
+struct dla_task {
+	/* platform specific data to communicate with portability layer */
+	void *task_data;
+	/* task state */
+	uint32_t state;
+	/* Task base address */
+	uint64_t base;
+	/* start address of a list of dla_operation_container */
+	uint64_t operation_desc_addr;
+	/* start address of a list of dla_surface_container */
+	uint64_t surface_desc_addr;
+	/* start address of a list of dla_common_op_desc */
+	uint64_t dependency_graph_addr;
+	/* start address of a list of dla_lut_param */
+	uint64_t lut_data_addr;
+	/*
+	 * start address of a list of dla_roi_desc,
+	 * the first one is dla_roi_array_desc
+	 * valid when network.dynamic_roi is true
+	 */
+	uint64_t roi_array_addr;
+	/* start address of a list of dla_surface_container */
+	uint64_t surface_addr;
+	/* start address of a list of dla_stat_container */
+	uint64_t stat_data_addr;
+} __packed __aligned(256);
+
+/**
+ * @brief			Configuration parameters supported by the engine
+ *
+ * atom_size			Memory smallest access size
+ * bdma_enable			Defines whether bdma is supported
+ * rubik_enable			Defines whether rubik is supported
+ * weight_compress_support	Defines whether weight data compression is supported
+ */
+struct dla_config {
+	uint32_t atom_size;
+	bool bdma_enable;
+	bool rubik_enable;
+	bool weight_compress_support;
+};
+
+#endif
diff --git a/drivers/nvdla/include/nvdla_interface.h b/drivers/nvdla/include/nvdla_interface.h
new file mode 100644
index 000000000000..7ad40b4c3db0
--- /dev/null
+++ b/drivers/nvdla/include/nvdla_interface.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NVDLA_INTERFACE_H_
+#define __NVDLA_INTERFACE_H_
+
+#include <linux/types.h>
+
+/**
+ * @brief			Register driver to firmware
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function must be called once during boot to initialize DLA
+ * engine scheduler and register driver with firmware before submitting
+ * any task. Pass pointer to driver context in @param driver_context
+ * which is passed as param when firmware calls any function
+ * of portability layer. It also updates pointer to engine context
+ * which must be passed in any function call to firmware after this point.
+ *
+ * @param engine_context	Pointer to engine specific data
+ * @param driver_context	Pointer to driver specific data
+ *
+ * @return			0 on success and negative on error
+ */
+int32_t dla_register_driver(void **engine_context, void *driver_context);
+
+/**
+ * @brief			Interrupt handler
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function is called when DLA interrupt is received. Portability layer
+ * should register it's own handler using the mechanism supported by that platform
+ * and call this function from the handler. Call to this function must be
+ * protected by lock to prevent handling interrupt when firmware is programming
+ * layers in process context.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ *
+ * @return			0 on success and negative on error
+ */
+int32_t dla_isr_handler(void *engine_context);
+
+/**
+ * @brief			Process events recorded in interrupt handler
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * Interrupt handler just records events and does not process those events.
+ * Portability layer must call this function in thread/process context after
+ * interrupt handler is done.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ * @param task_complete		Pointer to parameter to indicate task complete,
+				firmare writes 1 to it if all layers are processed.
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_process_events(void *engine_context, uint32_t *task_complete);
+
+/**
+ * @brief			Clear task from firmware
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function resets engine scheduler state including op descriptor cache,
+ * error values, sub-engine status, events etc and clears previous task state
+ * from firmware. This function can be called by portability layer after
+ * task completion. It is not mandatory to call it but calling it will
+ * ensure clean state before next task execution.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+void dla_clear_task(void *engine_context);
+
+/**
+ * @brief			Execute task
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function initializes sub-engines and starts task execution. Further
+ * programming and layer scheduling is triggered by events received from
+ * hardware.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ * @param task_data		Task specific data to be passed when reading task info
+ * @param config_data		Configuration data to be passed
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_execute_task(void *engine_context, void *task_data, void *config_data);
+
+/**
+ * @brief			Register read
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Read DLA HW register. Portability layer is responsible to use correct
+ * base address and for any IO mapping if required.
+ *
+ * @param engine_context	Driver specific data received in dla_register_driver
+ * @param addr			Register offset
+ *
+ * @return			Register value
+ *
+ */
+uint32_t dla_reg_read(void *driver_context, uint32_t addr);
+
+/**
+ * @brief			Register write
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Write DLA HW registr. Portability layer is responsible to use correct
+ * base address and for any IO mapping if required.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param addr			Register offset
+ * @param reg			Value to write
+ *
+ */
+void dla_reg_write(void *driver_context, uint32_t addr, uint32_t reg);
+
+/**
+ * @brief			Read data from DMA mapped memory in local buffer
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * This function reads data from buffers passed by UMD in local memory.
+ * Addresses for buffers passed by are shared in address list and network
+ * descriptor contains index in address list for those buffers. Firmware
+ * reads this data from buffer shared by UMD into local buffer to consume
+ * the information.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param task_data		Task specific data received in dla_execute_task
+ * @param src			Index in address list
+ * @param dst			Pointer to local memory
+ * @param size			Size of data to copy
+ * @param offset		Offset from start of UMD buffer
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_data_read(void *driver_context, void *task_data,
+				uint64_t src, void *dst,
+				uint32_t size, uint64_t offset);
+
+/**
+ * @brief			Write data to DMA mapped memory from local buffer
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * This function writes data from local buffer to buffer passed by UMD.
+ * Addresses for buffers passed by are shared in address list and network
+ * descriptor contains index in address list for those buffers. Firmware
+ * writes this data to buffer shared by UMD from local buffer to update
+ * the information.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param task_data		Task specific data received in dla_execute_task
+ * @param src			Pointer to local memory
+ * @param dst			Index in address list
+ * @param size			Size of data to copy
+ * @param offset		Offset from start of UMD buffer
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_data_write(void *driver_context, void *task_data,
+				void *src, uint64_t dst,
+				uint32_t size, uint64_t offset);
+
+/* Destination for DMA buffer */
+#define DESTINATION_PROCESSOR	0
+#define DESTINATION_DMA		1
+
+/**
+ * @brief			Read DMA address
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Some buffers shared by UMD are accessed by processor responsible for
+ * programming DLA HW. It would be companion micro-controller in case of
+ * headed config while main CPU in case of headless config. Also, some
+ * buffers are accessed by DLA DMA engines inside sub-engines. This function
+ * should return proper address accessible by destination user depending
+ * on config.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param task_data		Task specific data received in dla_execute_task
+ * @param index			Index in address list
+ * @param dst_ptr		Pointer to update address
+ * @param destination		Destination user for DMA address
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_get_dma_address(void *driver_context, void *task_data,
+					int16_t index, void *dst_ptr,
+					uint32_t destination);
+
+/**
+ * @brief			Read time value in micro-seconds
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Read system time in micro-seconds
+ *
+ * @return			Time value in micro-seconds
+ *
+ */
+int64_t dla_get_time_us(void);
+
+/**
+ * @brief			Print debug message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print debug message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_debug(const char *str, ...);
+
+/**
+ * @brief			Print information message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print information message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_info(const char *str, ...);
+
+/**
+ * @brief			Print warning message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print warning message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_warn(const char *str, ...);
+
+/**
+ * @brief			Print error message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print error message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_error(const char *str, ...);
+
+/**
+ * @brief			Fill memory region
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Fills the first len bytes of the memory area pointed to by src
+ * with the constant byte ch.
+ *
+ * @param src			Memory area address
+ * @param ch			Byte to fill
+ * @param len			Length of memory area to fill
+ *
+ * @return			Memory area address
+ *
+ */
+void *dla_memset(void *src, int ch, uint64_t len);
+
+/**
+ * @brief			Copy memory
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Copies len bytes from memory area src to memory area dest.
+ *
+ * @param dest			Destination memory area address
+ * @param src			Source memory area address
+ * @param len			Length of memory area to copy
+ *
+ * @return			Destination memory area address
+ *
+ */
+void *dla_memcpy(void *dest, const void *src, uint64_t len);
+
+#endif
diff --git a/drivers/nvdla/include/nvdla_ioctl.h b/drivers/nvdla/include/nvdla_ioctl.h
new file mode 100644
index 000000000000..3c8ec3a6cd51
--- /dev/null
+++ b/drivers/nvdla/include/nvdla_ioctl.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LINUX_NVDLA_IOCTL_H
+#define __LINUX_NVDLA_IOCTL_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#if !defined(__KERNEL__)
+#define __user
+#endif
+
+/**
+ * struct nvdla_mem_handle structure for memory handles
+ *
+ * @handle		handle to DMA buffer allocated in userspace
+ * @reserved		Reserved for padding
+ * @offset		offset in bytes from start address of buffer
+ *
+ */
+struct nvdla_mem_handle {
+	__u32 handle;
+	__u32 reserved;
+	__u64 offset;
+};
+
+/**
+ * struct nvdla_ioctl_submit_task structure for single task information
+ *
+ * @num_addresses		total number of entries in address_list
+ * @reserved			Reserved for padding
+ * @address_list		pointer to array of struct nvdla_mem_handle
+ *
+ */
+struct nvdla_ioctl_submit_task {
+#define NVDLA_MAX_BUFFERS_PER_TASK (6144)
+	__u32 num_addresses;
+#define NVDLA_NO_TIMEOUT    (0xffffffff)
+	__u32 timeout;
+	__u64 address_list;
+};
+
+/**
+ * struct nvdla_submit_args structure for task submit
+ *
+ * @tasks		pointer to array of struct nvdla_ioctl_submit_task
+ * @num_tasks		number of entries in tasks
+ * @flags		flags for task submit, no flags defined yet
+ * @version		version of task structure
+ *
+ */
+struct nvdla_submit_args {
+	__u64 tasks;
+	__u16 num_tasks;
+#define NVDLA_MAX_TASKS_PER_SUBMIT	24
+#define NVDLA_SUBMIT_FLAGS_ATOMIC	(1 << 0)
+	__u16 flags;
+	__u32 version;
+};
+
+/**
+ * struct nvdla_gem_create_args for allocating DMA buffer through GEM
+ *
+ * @handle		handle updated by kernel after allocation
+ * @flags		implementation specific flags
+ * @size		size of buffer to allocate
+ */
+struct nvdla_gem_create_args {
+	__u32 handle;
+	__u32 flags;
+	__u64 size;
+};
+
+/**
+ * struct nvdla_gem_map_offset_args for mapping DMA buffer
+ *
+ * @handle		handle of the buffer
+ * @reserved		reserved for padding
+ * @offset		offset updated by kernel after mapping
+ */
+struct nvdla_gem_map_offset_args {
+	__u32 handle;
+	__u32 reserved;
+	__u64 offset;
+};
+
+/**
+ * struct nvdla_gem_destroy_args for destroying DMA buffer
+ *
+ * @handle		handle of the buffer
+ */
+struct nvdla_gem_destroy_args {
+	__u32 handle;
+};
+
+#define DRM_NVDLA_SUBMIT		0x00
+#define DRM_NVDLA_GEM_CREATE		0x01
+#define DRM_NVDLA_GEM_MMAP		0x02
+#define DRM_NVDLA_GEM_DESTROY		0x03
+
+#define DRM_IOCTL_NVDLA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_SUBMIT, struct nvdla_submit_args)
+#define DRM_IOCTL_NVDLA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_CREATE, struct nvdla_gem_create_args)
+#define DRM_IOCTL_NVDLA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_MMAP, struct nvdla_gem_map_offset_args)
+#define DRM_IOCTL_NVDLA_GEM_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_DESTROY, struct nvdla_gem_destroy_args)
+
+#endif
diff --git a/drivers/nvdla/include/nvdla_linux.h b/drivers/nvdla/include/nvdla_linux.h
new file mode 100644
index 000000000000..2fc543dfa1c4
--- /dev/null
+++ b/drivers/nvdla/include/nvdla_linux.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LINUX_NVDLA_LINUX_H_
+#define __LINUX_NVDLA_LINUX_H_
+
+#include <linux/completion.h>
+#include <linux/device.h>
+#include <linux/kref.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+/**
+ * @brief			Task information submitted from user space
+ *
+ * ref				Reference count for task
+ * num_addresses		Number of addresses in address list
+ * nvdla_dev			Pointer to NVDLA device
+ * address_list			Address list
+ * file				DRM file instance
+ */
+struct nvdla_task {
+	struct kref ref;
+	uint32_t num_addresses;
+	struct nvdla_device *nvdla_dev;
+	struct nvdla_mem_handle *address_list;
+	struct drm_file *file;
+};
+
+/**
+ * @brief			Configuration parameters supported by the engine
+ *
+ * atom_size			Memory smallest access size
+ * bdma_enable			Defines whether bdma is supported
+ * rubik_enable			Defines whether rubik is supported
+ * weight_compress_support	Defines whether weight data compression is supported
+ */
+struct nvdla_config
+{
+	uint32_t atom_size;
+	bool bdma_enable;
+	bool rubik_enable;
+	bool weight_compress_support;
+};
+
+/**
+ * @brief			NVDLA device
+ *
+ * irq				Interrupt number associated with this device
+ * ref				Reference count for device
+ * base				IO mapped base address for device
+ * nvdla_lock			Spinlock used for synchronization
+ * drm				DRM device instance
+ * task				Pointer to task in execution
+ * config_data			Pointer to the configuration data
+ * pdev				Pointer to NVDLA platform device
+ * event_notifier		Completion object used to wait for events from HW
+ * engine_context		Private data passed from engine in dla_engine_init
+ */
+struct nvdla_device {
+	int32_t irq;
+	struct kref ref;
+	void __iomem *base;
+	spinlock_t nvdla_lock;
+	struct drm_device *drm;
+	struct nvdla_task *task;
+	struct nvdla_config *config_data;
+	struct platform_device *pdev;
+	struct completion event_notifier;
+
+	void *engine_context;
+};
+
+/**
+ * @brief			Submit task
+ *
+ * This function submits task to NVDLA engine.
+ *
+ * @param nvdla_dev		Pointer to NVDLA device
+ * @param task			Pointer to task
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t nvdla_task_submit(struct nvdla_device *nvdla_dev, struct nvdla_task *task);
+
+/**
+ * @brief			Get DMA address
+ *
+ * This function gets DMA address for given fd
+ *
+ * @param dev			DRM device instance
+ * @param file			DRM file instance
+ * @param fd			File desriptor for DMA buffer
+ * @param addr			Pointer to update DMA address
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t nvdla_gem_dma_addr(struct drm_device *dev, struct drm_file *file,
+					uint32_t fd, dma_addr_t *addr);
+
+/**
+ * @brief			DRM probe
+ *
+ * Probe function for DRM device
+ *
+ * @param nvdla_dev		NVDLA device pointer
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t nvdla_drm_probe(struct nvdla_device *nvdla_dev);
+
+/**
+ * @brief			DRM remove
+ *
+ * Remove function for DRM device
+ *
+ * @param nvdla_dev		NVDLA device pointer
+ *
+ */
+void nvdla_drm_remove(struct nvdla_device *nvdla_dev);
+
+#endif
diff --git a/drivers/nvdla/include/opendla.h b/drivers/nvdla/include/opendla.h
new file mode 100644
index 000000000000..41d7e30fb10d
--- /dev/null
+++ b/drivers/nvdla/include/opendla.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __OPENDLA_H_
+#define __OPENDLA_H_
+
+#define DLA_2_CONFIG
+#define CONFIG_NVDLA_NEED_FLUSH
+
+#ifdef DLA_2_CONFIG
+#include <opendla_small.h>
+#else
+#include <opendla_initial.h>
+#endif
+
+#ifdef CONFIG_NVDLA_NEED_FLUSH
+#include <soc/starfive/vic7100.h>
+#define nvdla_flush_dcache starfive_flush_dcache
+#else
+#define nvdla_flush_dcache
+#endif
+
+#endif
diff --git a/drivers/nvdla/include/opendla_initial.h b/drivers/nvdla/include/opendla_initial.h
new file mode 100644
index 000000000000..71335438f5d4
--- /dev/null
+++ b/drivers/nvdla/include/opendla_initial.h
@@ -0,0 +1,16743 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARNVDLA_H_
+#define __ARNVDLA_H_
+
+// Register GLB_S_NVDLA_HW_VERSION_0
+#define GLB_S_NVDLA_HW_VERSION_0                           (_MK_ADDR_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_SECURE                                    (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_DUAL                                      (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_SCR                                         (0)
+#define GLB_S_NVDLA_HW_VERSION_0_WORD_COUNT                                (0x1)
+#define GLB_S_NVDLA_HW_VERSION_0_RESET_VAL            (_MK_MASK_CONST(0x303031))
+#define GLB_S_NVDLA_HW_VERSION_0_RESET_MASK           (_MK_MASK_CONST(0xffffff))
+#define GLB_S_NVDLA_HW_VERSION_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_READ_MASK            (_MK_MASK_CONST(0xffffff))
+#define GLB_S_NVDLA_HW_VERSION_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT                (_MK_SHIFT_CONST(0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD \
+	(_MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_RANGE                               (7:0)
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_WOFFSET                             (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_DEFAULT            (_MK_MASK_CONST(0x31))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_DEFAULT_MASK       (_MK_MASK_CONST(0xff))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT                (_MK_SHIFT_CONST(8))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD \
+	(_MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_RANGE                              (23:8)
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_WOFFSET                             (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_DEFAULT          (_MK_MASK_CONST(0x3030))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register GLB_S_INTR_MASK_0
+#define GLB_S_INTR_MASK_0                                  (_MK_ADDR_CONST(0x4))
+#define GLB_S_INTR_MASK_0_SECURE                                           (0x0)
+#define GLB_S_INTR_MASK_0_DUAL                                             (0x0)
+#define GLB_S_INTR_MASK_0_SCR                                                (0)
+#define GLB_S_INTR_MASK_0_WORD_COUNT                                       (0x1)
+#define GLB_S_INTR_MASK_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RESET_MASK                  (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_MASK_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_READ_MASK                   (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_MASK_0_WRITE_MASK                  (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_RANGE                             (0:0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(1))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_RANGE                             (1:1)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(2))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_RANGE                             (2:2)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(3))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_RANGE                             (3:3)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(4))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_RANGE                             (4:4)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(5))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_RANGE                             (5:5)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT             (_MK_SHIFT_CONST(6))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_RANGE                            (6:6)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT             (_MK_SHIFT_CONST(7))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_RANGE                            (7:7)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT            (_MK_SHIFT_CONST(8))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_RANGE                           (8:8)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_WOFFSET                         (0x0)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT            (_MK_SHIFT_CONST(9))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_RANGE                           (9:9)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_WOFFSET                         (0x0)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT        (_MK_SHIFT_CONST(16))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_RANGE                      (16:16)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_WOFFSET                      (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT        (_MK_SHIFT_CONST(17))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_RANGE                      (17:17)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_WOFFSET                      (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT         (_MK_SHIFT_CONST(18))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_RANGE                       (18:18)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_WOFFSET                       (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT         (_MK_SHIFT_CONST(19))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_RANGE                       (19:19)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_WOFFSET                       (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT            (_MK_SHIFT_CONST(20))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_RANGE                          (20:20)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT            (_MK_SHIFT_CONST(21))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_RANGE                          (21:21)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register GLB_S_INTR_SET_0
+#define GLB_S_INTR_SET_0                                   (_MK_ADDR_CONST(0x8))
+#define GLB_S_INTR_SET_0_SECURE                                            (0x0)
+#define GLB_S_INTR_SET_0_DUAL                                              (0x0)
+#define GLB_S_INTR_SET_0_SCR                                                 (0)
+#define GLB_S_INTR_SET_0_WORD_COUNT                                        (0x1)
+#define GLB_S_INTR_SET_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RESET_MASK                   (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_SET_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_READ_MASK                         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_WRITE_MASK                   (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_RANGE                               (0:0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(1))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_RANGE                               (1:1)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(2))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_RANGE                               (2:2)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(3))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_RANGE                               (3:3)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(4))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_RANGE                               (4:4)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(5))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_RANGE                               (5:5)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT               (_MK_SHIFT_CONST(6))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_RANGE                              (6:6)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT               (_MK_SHIFT_CONST(7))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_RANGE                              (7:7)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT              (_MK_SHIFT_CONST(8))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_RANGE                             (8:8)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_WOFFSET                           (0x0)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT              (_MK_SHIFT_CONST(9))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_RANGE                             (9:9)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_WOFFSET                           (0x0)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT          (_MK_SHIFT_CONST(16))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_RANGE                        (16:16)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_WOFFSET                        (0x0)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT          (_MK_SHIFT_CONST(17))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_RANGE                        (17:17)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_WOFFSET                        (0x0)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT           (_MK_SHIFT_CONST(18))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_RANGE                         (18:18)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_WOFFSET                         (0x0)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT           (_MK_SHIFT_CONST(19))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_RANGE                         (19:19)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_WOFFSET                         (0x0)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT              (_MK_SHIFT_CONST(20))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_RANGE                            (20:20)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT              (_MK_SHIFT_CONST(21))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_RANGE                            (21:21)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register GLB_S_INTR_STATUS_0
+#define GLB_S_INTR_STATUS_0                                (_MK_ADDR_CONST(0xc))
+#define GLB_S_INTR_STATUS_0_SECURE                                         (0x0)
+#define GLB_S_INTR_STATUS_0_DUAL                                           (0x0)
+#define GLB_S_INTR_STATUS_0_SCR                                              (0)
+#define GLB_S_INTR_STATUS_0_WORD_COUNT                                     (0x1)
+#define GLB_S_INTR_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RESET_MASK                (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_READ_MASK                 (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_STATUS_0_WRITE_MASK                (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_RANGE                         (0:0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(1))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_RANGE                         (1:1)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(2))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_RANGE                         (2:2)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(3))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_RANGE                         (3:3)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(4))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_RANGE                         (4:4)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(5))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_RANGE                         (5:5)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT         (_MK_SHIFT_CONST(6))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_RANGE                        (6:6)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT         (_MK_SHIFT_CONST(7))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_RANGE                        (7:7)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT        (_MK_SHIFT_CONST(8))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_RANGE                       (8:8)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_WOFFSET                     (0x0)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT        (_MK_SHIFT_CONST(9))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_RANGE                       (9:9)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_WOFFSET                     (0x0)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT    (_MK_SHIFT_CONST(16))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_RANGE                  (16:16)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_WOFFSET                  (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT    (_MK_SHIFT_CONST(17))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_RANGE                  (17:17)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_WOFFSET                  (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT     (_MK_SHIFT_CONST(18))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_RANGE                   (18:18)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_WOFFSET                   (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT     (_MK_SHIFT_CONST(19))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_RANGE                   (19:19)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_WOFFSET                   (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT        (_MK_SHIFT_CONST(20))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_RANGE                      (20:20)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT        (_MK_SHIFT_CONST(21))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_RANGE                      (21:21)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_RD_WEIGHT_0_0
+#define MCIF_CFG_RD_WEIGHT_0_0                          (_MK_ADDR_CONST(0x2000))
+#define MCIF_CFG_RD_WEIGHT_0_0_SECURE                                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_DUAL                                        (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_SCR                                           (0)
+#define MCIF_CFG_RD_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_RD_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_RD_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_RANGE                        (7:0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_RANGE                        (15:8)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_RANGE                       (23:16)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_RANGE                       (31:24)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_RD_WEIGHT_1_0
+#define MCIF_CFG_RD_WEIGHT_1_0                          (_MK_ADDR_CONST(0x2004))
+#define MCIF_CFG_RD_WEIGHT_1_0_SECURE                                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_DUAL                                        (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_SCR                                           (0)
+#define MCIF_CFG_RD_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_RD_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_RD_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT        (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_RANGE                       (7:0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT        (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_RANGE                      (15:8)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT       (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_RANGE                     (23:16)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT    (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_RANGE                  (31:24)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_WOFFSET                  (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_RD_WEIGHT_2_0
+#define MCIF_CFG_RD_WEIGHT_2_0                          (_MK_ADDR_CONST(0x2008))
+#define MCIF_CFG_RD_WEIGHT_2_0_SECURE                                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_DUAL                                        (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_SCR                                           (0)
+#define MCIF_CFG_RD_WEIGHT_2_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_RD_WEIGHT_2_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_RD_WEIGHT_2_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_2_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT      (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_RANGE                     (7:0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_WOFFSET                   (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_RANGE                        (15:8)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_RANGE                     (23:16)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_RANGE                     (31:24)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_WR_WEIGHT_0_0
+#define MCIF_CFG_WR_WEIGHT_0_0                          (_MK_ADDR_CONST(0x200c))
+#define MCIF_CFG_WR_WEIGHT_0_0_SECURE                                      (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_DUAL                                        (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_SCR                                           (0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_WR_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_WR_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_RANGE                        (7:0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_RANGE                        (15:8)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_RANGE                       (23:16)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_RANGE                       (31:24)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_WR_WEIGHT_1_0
+#define MCIF_CFG_WR_WEIGHT_1_0                          (_MK_ADDR_CONST(0x2010))
+#define MCIF_CFG_WR_WEIGHT_1_0_SECURE                                      (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_DUAL                                        (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_SCR                                           (0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_WR_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_WR_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_RANGE                         (7:0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT        (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_RANGE                      (15:8)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_WOFFSET                     (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_RANGE                     (23:16)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_RANGE                     (31:24)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_OUTSTANDING_CNT_0
+#define MCIF_CFG_OUTSTANDING_CNT_0                      (_MK_ADDR_CONST(0x2014))
+#define MCIF_CFG_OUTSTANDING_CNT_0_SECURE                                  (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_DUAL                                    (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_SCR                                       (0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_WORD_COUNT                              (0x1)
+#define MCIF_CFG_OUTSTANDING_CNT_0_RESET_VAL            (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_READ_MASK            (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_RANGE                         (7:0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_WOFFSET                       (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_RANGE                        (15:8)
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_WOFFSET                       (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_STATUS_0
+#define MCIF_STATUS_0                                   (_MK_ADDR_CONST(0x2018))
+#define MCIF_STATUS_0_SECURE                                               (0x0)
+#define MCIF_STATUS_0_DUAL                                                 (0x0)
+#define MCIF_STATUS_0_SCR                                                    (0)
+#define MCIF_STATUS_0_WORD_COUNT                                           (0x1)
+#define MCIF_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x100))
+#define MCIF_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x100))
+#define MCIF_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x100))
+#define MCIF_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
+#define MCIF_STATUS_0_IDLE_FIELD \
+	(_MK_FIELD_CONST(0x1, MCIF_STATUS_0_IDLE_SHIFT))
+#define MCIF_STATUS_0_IDLE_RANGE                                           (8:8)
+#define MCIF_STATUS_0_IDLE_WOFFSET                                         (0x0)
+#define MCIF_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
+#define MCIF_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
+#define MCIF_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
+#define MCIF_STATUS_0_IDLE_INIT_ENUM                                       (YES)
+#define MCIF_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
+#define MCIF_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
+
+
+// Register CVIF_CFG_RD_WEIGHT_0_0
+#define CVIF_CFG_RD_WEIGHT_0_0                          (_MK_ADDR_CONST(0x3000))
+#define CVIF_CFG_RD_WEIGHT_0_0_SECURE                                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_DUAL                                        (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_SCR                                           (0)
+#define CVIF_CFG_RD_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_RD_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_RD_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_RANGE                        (7:0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_RANGE                        (15:8)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_RANGE                       (23:16)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_RANGE                       (31:24)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_RD_WEIGHT_1_0
+#define CVIF_CFG_RD_WEIGHT_1_0                          (_MK_ADDR_CONST(0x3004))
+#define CVIF_CFG_RD_WEIGHT_1_0_SECURE                                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_DUAL                                        (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_SCR                                           (0)
+#define CVIF_CFG_RD_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_RD_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_RD_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT        (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_RANGE                       (7:0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT        (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_RANGE                      (15:8)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT       (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_RANGE                     (23:16)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT    (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_RANGE                  (31:24)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_WOFFSET                  (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_RD_WEIGHT_2_0
+#define CVIF_CFG_RD_WEIGHT_2_0                          (_MK_ADDR_CONST(0x3008))
+#define CVIF_CFG_RD_WEIGHT_2_0_SECURE                                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_DUAL                                        (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_SCR                                           (0)
+#define CVIF_CFG_RD_WEIGHT_2_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_RD_WEIGHT_2_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_RD_WEIGHT_2_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_2_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT      (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_RANGE                     (7:0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_WOFFSET                   (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_RANGE                        (15:8)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_RANGE                     (23:16)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_RANGE                     (31:24)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_WR_WEIGHT_0_0
+#define CVIF_CFG_WR_WEIGHT_0_0                          (_MK_ADDR_CONST(0x300c))
+#define CVIF_CFG_WR_WEIGHT_0_0_SECURE                                      (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_DUAL                                        (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_SCR                                           (0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_WR_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_WR_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_RANGE                        (7:0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_RANGE                        (15:8)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_RANGE                       (23:16)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_RANGE                       (31:24)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_WR_WEIGHT_1_0
+#define CVIF_CFG_WR_WEIGHT_1_0                          (_MK_ADDR_CONST(0x3010))
+#define CVIF_CFG_WR_WEIGHT_1_0_SECURE                                      (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_DUAL                                        (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_SCR                                           (0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_WR_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_WR_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_RANGE                         (7:0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT        (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_RANGE                      (15:8)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_WOFFSET                     (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_RANGE                     (23:16)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_RANGE                     (31:24)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_OUTSTANDING_CNT_0
+#define CVIF_CFG_OUTSTANDING_CNT_0                      (_MK_ADDR_CONST(0x3014))
+#define CVIF_CFG_OUTSTANDING_CNT_0_SECURE                                  (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_DUAL                                    (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_SCR                                       (0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_WORD_COUNT                              (0x1)
+#define CVIF_CFG_OUTSTANDING_CNT_0_RESET_VAL            (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_READ_MASK            (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_RANGE                         (7:0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_WOFFSET                       (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_RANGE                        (15:8)
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_WOFFSET                       (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_STATUS_0
+#define CVIF_STATUS_0                                   (_MK_ADDR_CONST(0x3018))
+#define CVIF_STATUS_0_SECURE                                               (0x0)
+#define CVIF_STATUS_0_DUAL                                                 (0x0)
+#define CVIF_STATUS_0_SCR                                                    (0)
+#define CVIF_STATUS_0_WORD_COUNT                                           (0x1)
+#define CVIF_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x100))
+#define CVIF_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x100))
+#define CVIF_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x100))
+#define CVIF_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
+#define CVIF_STATUS_0_IDLE_FIELD \
+	(_MK_FIELD_CONST(0x1, CVIF_STATUS_0_IDLE_SHIFT))
+#define CVIF_STATUS_0_IDLE_RANGE                                           (8:8)
+#define CVIF_STATUS_0_IDLE_WOFFSET                                         (0x0)
+#define CVIF_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
+#define CVIF_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
+#define CVIF_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
+#define CVIF_STATUS_0_IDLE_INIT_ENUM                                       (YES)
+#define CVIF_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
+#define CVIF_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_SRC_ADDR_LOW_0
+#define BDMA_CFG_SRC_ADDR_LOW_0                         (_MK_ADDR_CONST(0x4000))
+#define BDMA_CFG_SRC_ADDR_LOW_0_SECURE                                     (0x0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_DUAL                                       (0x0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_SCR                                          (0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_WORD_COUNT                                 (0x1)
+#define BDMA_CFG_SRC_ADDR_LOW_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT                   (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_RANGE                                 (31:5)
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_WOFFSET                                (0x0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_DEFAULT_MASK     (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SRC_ADDR_HIGH_0
+#define BDMA_CFG_SRC_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x4004))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SECURE                                    (0x0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_DUAL                                      (0x0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SCR                                         (0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_WORD_COUNT                                (0x1)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT                   (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_RANGE                                 (31:0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_WOFFSET                                (0x0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_ADDR_LOW_0
+#define BDMA_CFG_DST_ADDR_LOW_0                         (_MK_ADDR_CONST(0x4008))
+#define BDMA_CFG_DST_ADDR_LOW_0_SECURE                                     (0x0)
+#define BDMA_CFG_DST_ADDR_LOW_0_DUAL                                       (0x0)
+#define BDMA_CFG_DST_ADDR_LOW_0_SCR                                          (0)
+#define BDMA_CFG_DST_ADDR_LOW_0_WORD_COUNT                                 (0x1)
+#define BDMA_CFG_DST_ADDR_LOW_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_ADDR_LOW_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_ADDR_LOW_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT                   (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_RANGE                                 (31:5)
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_WOFFSET                                (0x0)
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_DEFAULT_MASK     (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_ADDR_HIGH_0
+#define BDMA_CFG_DST_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x400c))
+#define BDMA_CFG_DST_ADDR_HIGH_0_SECURE                                    (0x0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_DUAL                                      (0x0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_SCR                                         (0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_WORD_COUNT                                (0x1)
+#define BDMA_CFG_DST_ADDR_HIGH_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT                   (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_RANGE                                 (31:0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_WOFFSET                                (0x0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_LINE_0
+#define BDMA_CFG_LINE_0                                 (_MK_ADDR_CONST(0x4010))
+#define BDMA_CFG_LINE_0_SECURE                                             (0x0)
+#define BDMA_CFG_LINE_0_DUAL                                               (0x0)
+#define BDMA_CFG_LINE_0_SCR                                                  (0)
+#define BDMA_CFG_LINE_0_WORD_COUNT                                         (0x1)
+#define BDMA_CFG_LINE_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_RESET_MASK                      (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_READ_MASK                       (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_SIZE_SHIFT                          (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LINE_0_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT))
+#define BDMA_CFG_LINE_0_SIZE_RANGE                                        (12:0)
+#define BDMA_CFG_LINE_0_SIZE_WOFFSET                                       (0x0)
+#define BDMA_CFG_LINE_0_SIZE_DEFAULT                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_DEFAULT_MASK               (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_SIZE_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_CMD_0
+#define BDMA_CFG_CMD_0                                  (_MK_ADDR_CONST(0x4014))
+#define BDMA_CFG_CMD_0_SECURE                                              (0x0)
+#define BDMA_CFG_CMD_0_DUAL                                                (0x0)
+#define BDMA_CFG_CMD_0_SCR                                                   (0)
+#define BDMA_CFG_CMD_0_WORD_COUNT                                          (0x1)
+#define BDMA_CFG_CMD_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_RESET_MASK                          (_MK_MASK_CONST(0x3))
+#define BDMA_CFG_CMD_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_READ_MASK                           (_MK_MASK_CONST(0x3))
+#define BDMA_CFG_CMD_0_WRITE_MASK                          (_MK_MASK_CONST(0x3))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_RANGE                                  (0:0)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_WOFFSET                                (0x0)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM                   (_MK_ENUM_CONST(0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC                       (_MK_ENUM_CONST(1))
+
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT                   (_MK_SHIFT_CONST(1))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_RANGE                                  (1:1)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_WOFFSET                                (0x0)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM                   (_MK_ENUM_CONST(0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC                       (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_LINE_REPEAT_0
+#define BDMA_CFG_LINE_REPEAT_0                          (_MK_ADDR_CONST(0x4018))
+#define BDMA_CFG_LINE_REPEAT_0_SECURE                                      (0x0)
+#define BDMA_CFG_LINE_REPEAT_0_DUAL                                        (0x0)
+#define BDMA_CFG_LINE_REPEAT_0_SCR                                           (0)
+#define BDMA_CFG_LINE_REPEAT_0_WORD_COUNT                                  (0x1)
+#define BDMA_CFG_LINE_REPEAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_RESET_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_READ_MASK              (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_RANGE                               (23:0)
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_WOFFSET                              (0x0)
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_DEFAULT_MASK    (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SRC_LINE_0
+#define BDMA_CFG_SRC_LINE_0                             (_MK_ADDR_CONST(0x401c))
+#define BDMA_CFG_SRC_LINE_0_SECURE                                         (0x0)
+#define BDMA_CFG_SRC_LINE_0_DUAL                                           (0x0)
+#define BDMA_CFG_SRC_LINE_0_SCR                                              (0)
+#define BDMA_CFG_SRC_LINE_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_SRC_LINE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_LINE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_LINE_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_SRC_LINE_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_SRC_LINE_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_LINE_0
+#define BDMA_CFG_DST_LINE_0                             (_MK_ADDR_CONST(0x4020))
+#define BDMA_CFG_DST_LINE_0_SECURE                                         (0x0)
+#define BDMA_CFG_DST_LINE_0_DUAL                                           (0x0)
+#define BDMA_CFG_DST_LINE_0_SCR                                              (0)
+#define BDMA_CFG_DST_LINE_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_DST_LINE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_LINE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_LINE_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT))
+#define BDMA_CFG_DST_LINE_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_DST_LINE_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_DST_LINE_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_DST_LINE_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SURF_REPEAT_0
+#define BDMA_CFG_SURF_REPEAT_0                          (_MK_ADDR_CONST(0x4024))
+#define BDMA_CFG_SURF_REPEAT_0_SECURE                                      (0x0)
+#define BDMA_CFG_SURF_REPEAT_0_DUAL                                        (0x0)
+#define BDMA_CFG_SURF_REPEAT_0_SCR                                           (0)
+#define BDMA_CFG_SURF_REPEAT_0_WORD_COUNT                                  (0x1)
+#define BDMA_CFG_SURF_REPEAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_RESET_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_READ_MASK              (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_RANGE                               (23:0)
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_WOFFSET                              (0x0)
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_DEFAULT_MASK    (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SRC_SURF_0
+#define BDMA_CFG_SRC_SURF_0                             (_MK_ADDR_CONST(0x4028))
+#define BDMA_CFG_SRC_SURF_0_SECURE                                         (0x0)
+#define BDMA_CFG_SRC_SURF_0_DUAL                                           (0x0)
+#define BDMA_CFG_SRC_SURF_0_SCR                                              (0)
+#define BDMA_CFG_SRC_SURF_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_SRC_SURF_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_SURF_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_SURF_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_SRC_SURF_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_SRC_SURF_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_SURF_0
+#define BDMA_CFG_DST_SURF_0                             (_MK_ADDR_CONST(0x402c))
+#define BDMA_CFG_DST_SURF_0_SECURE                                         (0x0)
+#define BDMA_CFG_DST_SURF_0_DUAL                                           (0x0)
+#define BDMA_CFG_DST_SURF_0_SCR                                              (0)
+#define BDMA_CFG_DST_SURF_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_DST_SURF_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_SURF_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_SURF_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT))
+#define BDMA_CFG_DST_SURF_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_DST_SURF_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_DST_SURF_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_DST_SURF_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_OP_0
+#define BDMA_CFG_OP_0                                   (_MK_ADDR_CONST(0x4030))
+#define BDMA_CFG_OP_0_SECURE                                               (0x0)
+#define BDMA_CFG_OP_0_DUAL                                                 (0x0)
+#define BDMA_CFG_OP_0_SCR                                                    (0)
+#define BDMA_CFG_OP_0_WORD_COUNT                                           (0x1)
+#define BDMA_CFG_OP_0_RESET_VAL                            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_RESET_MASK                           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_READ_MASK                            (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_WRITE_MASK                           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_EN_SHIFT                              (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_OP_0_EN_FIELD    (_MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT))
+#define BDMA_CFG_OP_0_EN_RANGE                                             (0:0)
+#define BDMA_CFG_OP_0_EN_WOFFSET                                           (0x0)
+#define BDMA_CFG_OP_0_EN_DEFAULT                           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_DEFAULT_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_EN_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_EN_DISABLE                             (_MK_ENUM_CONST(0))
+#define BDMA_CFG_OP_0_EN_ENABLE                              (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_LAUNCH0_0
+#define BDMA_CFG_LAUNCH0_0                              (_MK_ADDR_CONST(0x4034))
+#define BDMA_CFG_LAUNCH0_0_SECURE                                          (0x0)
+#define BDMA_CFG_LAUNCH0_0_DUAL                                            (0x0)
+#define BDMA_CFG_LAUNCH0_0_SCR                                               (0)
+#define BDMA_CFG_LAUNCH0_0_WORD_COUNT                                      (0x1)
+#define BDMA_CFG_LAUNCH0_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT                (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_RANGE                               (0:0)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_WOFFSET                             (0x0)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO                    (_MK_ENUM_CONST(0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES                   (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_LAUNCH1_0
+#define BDMA_CFG_LAUNCH1_0                              (_MK_ADDR_CONST(0x4038))
+#define BDMA_CFG_LAUNCH1_0_SECURE                                          (0x0)
+#define BDMA_CFG_LAUNCH1_0_DUAL                                            (0x0)
+#define BDMA_CFG_LAUNCH1_0_SCR                                               (0)
+#define BDMA_CFG_LAUNCH1_0_WORD_COUNT                                      (0x1)
+#define BDMA_CFG_LAUNCH1_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT                (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_RANGE                               (0:0)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_WOFFSET                             (0x0)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO                    (_MK_ENUM_CONST(0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES                   (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_STATUS_0
+#define BDMA_CFG_STATUS_0                               (_MK_ADDR_CONST(0x403c))
+#define BDMA_CFG_STATUS_0_SECURE                                           (0x0)
+#define BDMA_CFG_STATUS_0_DUAL                                             (0x0)
+#define BDMA_CFG_STATUS_0_SCR                                                (0)
+#define BDMA_CFG_STATUS_0_WORD_COUNT                                       (0x1)
+#define BDMA_CFG_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT              (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_RANGE                             (0:0)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_WOFFSET                           (0x0)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_DEFAULT           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_INIT_ENUM                          (NO)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO                  (_MK_ENUM_CONST(0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES                 (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_STATUS_0
+#define BDMA_STATUS_0                                   (_MK_ADDR_CONST(0x4040))
+#define BDMA_STATUS_0_SECURE                                               (0x0)
+#define BDMA_STATUS_0_DUAL                                                 (0x0)
+#define BDMA_STATUS_0_SCR                                                    (0)
+#define BDMA_STATUS_0_WORD_COUNT                                           (0x1)
+#define BDMA_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x114))
+#define BDMA_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x7ff))
+#define BDMA_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x7ff))
+#define BDMA_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_SHIFT                       (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_0_FREE_SLOT_FIELD \
+	(_MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT))
+#define BDMA_STATUS_0_FREE_SLOT_RANGE                                      (7:0)
+#define BDMA_STATUS_0_FREE_SLOT_WOFFSET                                    (0x0)
+#define BDMA_STATUS_0_FREE_SLOT_DEFAULT                   (_MK_MASK_CONST(0x14))
+#define BDMA_STATUS_0_FREE_SLOT_DEFAULT_MASK              (_MK_MASK_CONST(0xff))
+#define BDMA_STATUS_0_FREE_SLOT_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+
+#define BDMA_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
+#define BDMA_STATUS_0_IDLE_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT))
+#define BDMA_STATUS_0_IDLE_RANGE                                           (8:8)
+#define BDMA_STATUS_0_IDLE_WOFFSET                                         (0x0)
+#define BDMA_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_IDLE_INIT_ENUM                                       (YES)
+#define BDMA_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
+#define BDMA_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
+
+#define BDMA_STATUS_0_GRP0_BUSY_SHIFT                       (_MK_SHIFT_CONST(9))
+#define BDMA_STATUS_0_GRP0_BUSY_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT))
+#define BDMA_STATUS_0_GRP0_BUSY_RANGE                                      (9:9)
+#define BDMA_STATUS_0_GRP0_BUSY_WOFFSET                                    (0x0)
+#define BDMA_STATUS_0_GRP0_BUSY_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP0_BUSY_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP0_BUSY_INIT_ENUM                                   (NO)
+#define BDMA_STATUS_0_GRP0_BUSY_NO                           (_MK_ENUM_CONST(0))
+#define BDMA_STATUS_0_GRP0_BUSY_YES                          (_MK_ENUM_CONST(1))
+
+#define BDMA_STATUS_0_GRP1_BUSY_SHIFT                      (_MK_SHIFT_CONST(10))
+#define BDMA_STATUS_0_GRP1_BUSY_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT))
+#define BDMA_STATUS_0_GRP1_BUSY_RANGE                                    (10:10)
+#define BDMA_STATUS_0_GRP1_BUSY_WOFFSET                                    (0x0)
+#define BDMA_STATUS_0_GRP1_BUSY_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP1_BUSY_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP1_BUSY_INIT_ENUM                                   (NO)
+#define BDMA_STATUS_0_GRP1_BUSY_NO                           (_MK_ENUM_CONST(0))
+#define BDMA_STATUS_0_GRP1_BUSY_YES                          (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_STATUS_GRP0_READ_STALL_0
+#define BDMA_STATUS_GRP0_READ_STALL_0                   (_MK_ADDR_CONST(0x4044))
+#define BDMA_STATUS_GRP0_READ_STALL_0_SECURE                               (0x0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_DUAL                                 (0x0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_SCR                                    (0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_WORD_COUNT                           (0x1)
+#define BDMA_STATUS_GRP0_READ_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_READ_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_READ_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT           (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_RANGE                         (31:0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_WOFFSET                        (0x0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_STATUS_GRP0_WRITE_STALL_0
+#define BDMA_STATUS_GRP0_WRITE_STALL_0                  (_MK_ADDR_CONST(0x4048))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SECURE                              (0x0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_DUAL                                (0x0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SCR                                   (0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_WORD_COUNT                          (0x1)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_RANGE                        (31:0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_WOFFSET                       (0x0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_STATUS_GRP1_READ_STALL_0
+#define BDMA_STATUS_GRP1_READ_STALL_0                   (_MK_ADDR_CONST(0x404c))
+#define BDMA_STATUS_GRP1_READ_STALL_0_SECURE                               (0x0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_DUAL                                 (0x0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_SCR                                    (0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_WORD_COUNT                           (0x1)
+#define BDMA_STATUS_GRP1_READ_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_READ_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_READ_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT           (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_RANGE                         (31:0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_WOFFSET                        (0x0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_STATUS_GRP1_WRITE_STALL_0
+#define BDMA_STATUS_GRP1_WRITE_STALL_0                  (_MK_ADDR_CONST(0x4050))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SECURE                              (0x0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_DUAL                                (0x0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SCR                                   (0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_WORD_COUNT                          (0x1)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_RANGE                        (31:0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_WOFFSET                       (0x0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_S_STATUS_0
+#define CDMA_S_STATUS_0                                 (_MK_ADDR_CONST(0x5000))
+#define CDMA_S_STATUS_0_SECURE                                             (0x0)
+#define CDMA_S_STATUS_0_DUAL                                               (0x0)
+#define CDMA_S_STATUS_0_SCR                                                  (0)
+#define CDMA_S_STATUS_0_WORD_COUNT                                         (0x1)
+#define CDMA_S_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_RESET_MASK                     (_MK_MASK_CONST(0x30003))
+#define CDMA_S_STATUS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_READ_MASK                      (_MK_MASK_CONST(0x30003))
+#define CDMA_S_STATUS_0_WRITE_MASK                         (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define CDMA_S_STATUS_0_STATUS_0_RANGE                                     (1:0)
+#define CDMA_S_STATUS_0_STATUS_0_WOFFSET                                   (0x0)
+#define CDMA_S_STATUS_0_STATUS_0_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CDMA_S_STATUS_0_STATUS_0_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDMA_S_STATUS_0_STATUS_0_INIT_ENUM                                (IDLE)
+#define CDMA_S_STATUS_0_STATUS_0_IDLE                        (_MK_ENUM_CONST(0))
+#define CDMA_S_STATUS_0_STATUS_0_RUNNING                     (_MK_ENUM_CONST(1))
+#define CDMA_S_STATUS_0_STATUS_0_PENDING                     (_MK_ENUM_CONST(2))
+
+#define CDMA_S_STATUS_0_STATUS_1_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define CDMA_S_STATUS_0_STATUS_1_RANGE                                   (17:16)
+#define CDMA_S_STATUS_0_STATUS_1_WOFFSET                                   (0x0)
+#define CDMA_S_STATUS_0_STATUS_1_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CDMA_S_STATUS_0_STATUS_1_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDMA_S_STATUS_0_STATUS_1_INIT_ENUM                                (IDLE)
+#define CDMA_S_STATUS_0_STATUS_1_IDLE                        (_MK_ENUM_CONST(0))
+#define CDMA_S_STATUS_0_STATUS_1_RUNNING                     (_MK_ENUM_CONST(1))
+#define CDMA_S_STATUS_0_STATUS_1_PENDING                     (_MK_ENUM_CONST(2))
+
+
+// Register CDMA_S_POINTER_0
+#define CDMA_S_POINTER_0                                (_MK_ADDR_CONST(0x5004))
+#define CDMA_S_POINTER_0_SECURE                                            (0x0)
+#define CDMA_S_POINTER_0_DUAL                                              (0x0)
+#define CDMA_S_POINTER_0_SCR                                                 (0)
+#define CDMA_S_POINTER_0_WORD_COUNT                                        (0x1)
+#define CDMA_S_POINTER_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_RESET_MASK                    (_MK_MASK_CONST(0x10001))
+#define CDMA_S_POINTER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_READ_MASK                     (_MK_MASK_CONST(0x10001))
+#define CDMA_S_POINTER_0_WRITE_MASK                        (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_PRODUCER_SHIFT                     (_MK_SHIFT_CONST(0))
+#define CDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define CDMA_S_POINTER_0_PRODUCER_RANGE                                    (0:0)
+#define CDMA_S_POINTER_0_PRODUCER_WOFFSET                                  (0x0)
+#define CDMA_S_POINTER_0_PRODUCER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_PRODUCER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_PRODUCER_INIT_ENUM                            (GROUP_0)
+#define CDMA_S_POINTER_0_PRODUCER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CDMA_S_POINTER_0_PRODUCER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+#define CDMA_S_POINTER_0_CONSUMER_SHIFT                    (_MK_SHIFT_CONST(16))
+#define CDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define CDMA_S_POINTER_0_CONSUMER_RANGE                                  (16:16)
+#define CDMA_S_POINTER_0_CONSUMER_WOFFSET                                  (0x0)
+#define CDMA_S_POINTER_0_CONSUMER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_CONSUMER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_CONSUMER_INIT_ENUM                            (GROUP_0)
+#define CDMA_S_POINTER_0_CONSUMER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CDMA_S_POINTER_0_CONSUMER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_S_ARBITER_0
+#define CDMA_S_ARBITER_0                                (_MK_ADDR_CONST(0x5008))
+#define CDMA_S_ARBITER_0_SECURE                                            (0x0)
+#define CDMA_S_ARBITER_0_DUAL                                              (0x0)
+#define CDMA_S_ARBITER_0_SCR                                                 (0)
+#define CDMA_S_ARBITER_0_WORD_COUNT                                        (0x1)
+#define CDMA_S_ARBITER_0_RESET_VAL                     (_MK_MASK_CONST(0x3000f))
+#define CDMA_S_ARBITER_0_RESET_MASK                    (_MK_MASK_CONST(0xf000f))
+#define CDMA_S_ARBITER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_READ_MASK                     (_MK_MASK_CONST(0xf000f))
+#define CDMA_S_ARBITER_0_WRITE_MASK                    (_MK_MASK_CONST(0xf000f))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_RANGE                                  (3:0)
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_WOFFSET                                (0x0)
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_DEFAULT                (_MK_MASK_CONST(0xf))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_DEFAULT_MASK           (_MK_MASK_CONST(0xf))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CDMA_S_ARBITER_0_ARB_WMB_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT))
+#define CDMA_S_ARBITER_0_ARB_WMB_RANGE                                   (19:16)
+#define CDMA_S_ARBITER_0_ARB_WMB_WOFFSET                                   (0x0)
+#define CDMA_S_ARBITER_0_ARB_WMB_DEFAULT                   (_MK_MASK_CONST(0x3))
+#define CDMA_S_ARBITER_0_ARB_WMB_DEFAULT_MASK              (_MK_MASK_CONST(0xf))
+#define CDMA_S_ARBITER_0_ARB_WMB_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WMB_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WMB_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WMB_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_S_CBUF_FLUSH_STATUS_0
+#define CDMA_S_CBUF_FLUSH_STATUS_0                      (_MK_ADDR_CONST(0x500c))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SECURE                                  (0x0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_DUAL                                    (0x0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SCR                                       (0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_WORD_COUNT                              (0x1)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_RESET_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_READ_MASK               (_MK_MASK_CONST(0x1))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_WRITE_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_RANGE                        (0:0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_WOFFSET                      (0x0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_OP_ENABLE_0
+#define CDMA_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x5010))
+#define CDMA_D_OP_ENABLE_0_SECURE                                          (0x0)
+#define CDMA_D_OP_ENABLE_0_DUAL                                            (0x0)
+#define CDMA_D_OP_ENABLE_0_SCR                                               (0)
+#define CDMA_D_OP_ENABLE_0_WORD_COUNT                                      (0x1)
+#define CDMA_D_OP_ENABLE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CDMA_D_OP_ENABLE_0_OP_EN_RANGE                                     (0:0)
+#define CDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                                   (0x0)
+#define CDMA_D_OP_ENABLE_0_OP_EN_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                             (DISABLE)
+#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE                     (_MK_ENUM_CONST(0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE                      (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_MISC_CFG_0
+#define CDMA_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x5014))
+#define CDMA_D_MISC_CFG_0_SECURE                                           (0x0)
+#define CDMA_D_MISC_CFG_0_DUAL                                             (0x0)
+#define CDMA_D_MISC_CFG_0_SCR                                                (0)
+#define CDMA_D_MISC_CFG_0_WORD_COUNT                                       (0x1)
+#define CDMA_D_MISC_CFG_0_RESET_VAL                     (_MK_MASK_CONST(0x1100))
+#define CDMA_D_MISC_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x11113301))
+#define CDMA_D_MISC_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x11113301))
+#define CDMA_D_MISC_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x11113301))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_RANGE                                  (0:0)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_WOFFSET                                (0x0)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                           (DIRECT)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT                   (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD                 (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT                (_MK_SHIFT_CONST(8))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_RANGE                               (9:8)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_WOFFSET                             (0x0)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_DEFAULT             (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK        (_MK_MASK_CONST(0x3))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                         (INT16)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8                  (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16                 (_MK_ENUM_CONST(1))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16                  (_MK_ENUM_CONST(2))
+
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT             (_MK_SHIFT_CONST(12))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_RANGE                           (13:12)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                           (0x0)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_DEFAULT           (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK      (_MK_MASK_CONST(0x3))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                       (INT16)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8                (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16               (_MK_ENUM_CONST(1))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16                (_MK_ENUM_CONST(2))
+
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT                 (_MK_SHIFT_CONST(16))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_RANGE                               (16:16)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_WOFFSET                               (0x0)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_INIT_ENUM                         (DISABLE)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE                 (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE                  (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT               (_MK_SHIFT_CONST(20))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_RANGE                             (20:20)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_WOFFSET                             (0x0)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_INIT_ENUM                       (DISABLE)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE               (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT              (_MK_SHIFT_CONST(24))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_RANGE                            (24:24)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_WOFFSET                            (0x0)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_INIT_ENUM                      (DISABLE)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE              (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE               (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT            (_MK_SHIFT_CONST(28))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_RANGE                          (28:28)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_WOFFSET                          (0x0)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_INIT_ENUM                    (DISABLE)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE            (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE             (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_DATAIN_FORMAT_0
+#define CDMA_D_DATAIN_FORMAT_0                          (_MK_ADDR_CONST(0x5018))
+#define CDMA_D_DATAIN_FORMAT_0_SECURE                                      (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_DUAL                                        (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_SCR                                           (0)
+#define CDMA_D_DATAIN_FORMAT_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DATAIN_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0xc00))
+#define CDMA_D_DATAIN_FORMAT_0_RESET_MASK             (_MK_MASK_CONST(0x113f01))
+#define CDMA_D_DATAIN_FORMAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_READ_MASK              (_MK_MASK_CONST(0x113f01))
+#define CDMA_D_DATAIN_FORMAT_0_WRITE_MASK             (_MK_MASK_CONST(0x113f01))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_RANGE                         (0:0)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_WOFFSET                       (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_INIT_ENUM                 (FEATURE)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE         (_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL           (_MK_ENUM_CONST(1))
+
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT           (_MK_SHIFT_CONST(8))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_RANGE                         (13:8)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_WOFFSET                        (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_DEFAULT        (_MK_MASK_CONST(0xc))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_INIT_ENUM               (T_A8B8G8R8)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8             (_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10            (_MK_ENUM_CONST(1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12            (_MK_ENUM_CONST(2))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16            (_MK_ENUM_CONST(3))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I          (_MK_ENUM_CONST(4))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F          (_MK_ENUM_CONST(5))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16 \
+	(_MK_ENUM_CONST(6))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16 \
+	(_MK_ENUM_CONST(7))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F \
+	(_MK_ENUM_CONST(8))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16 \
+	(_MK_ENUM_CONST(9))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16 \
+	(_MK_ENUM_CONST(10))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F \
+	(_MK_ENUM_CONST(11))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8      (_MK_ENUM_CONST(12))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8      (_MK_ENUM_CONST(13))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8      (_MK_ENUM_CONST(14))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8      (_MK_ENUM_CONST(15))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8      (_MK_ENUM_CONST(16))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8      (_MK_ENUM_CONST(17))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8      (_MK_ENUM_CONST(18))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8      (_MK_ENUM_CONST(19))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10 \
+	(_MK_ENUM_CONST(20))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10 \
+	(_MK_ENUM_CONST(21))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2 \
+	(_MK_ENUM_CONST(22))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2 \
+	(_MK_ENUM_CONST(23))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10 \
+	(_MK_ENUM_CONST(24))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2 \
+	(_MK_ENUM_CONST(25))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8      (_MK_ENUM_CONST(26))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8      (_MK_ENUM_CONST(27))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444 \
+	(_MK_ENUM_CONST(28))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444 \
+	(_MK_ENUM_CONST(29))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444 \
+	(_MK_ENUM_CONST(30))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444 \
+	(_MK_ENUM_CONST(31))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444 \
+	(_MK_ENUM_CONST(32))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444 \
+	(_MK_ENUM_CONST(33))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444 \
+	(_MK_ENUM_CONST(34))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444 \
+	(_MK_ENUM_CONST(35))
+
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RANGE                       (16:16)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_WOFFSET                       (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_INIT_ENUM            (PITCH_LINEAR)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR    (_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR \
+	(_MK_ENUM_CONST(1))
+
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_RANGE                 (20:20)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_WOFFSET                 (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_INIT_ENUM      (UNSIGNED_INT)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT \
+	(_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT \
+	(_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_DATAIN_SIZE_0_0
+#define CDMA_D_DATAIN_SIZE_0_0                          (_MK_ADDR_CONST(0x501c))
+#define CDMA_D_DATAIN_SIZE_0_0_SECURE                                      (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_DUAL                                        (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_SCR                                           (0)
+#define CDMA_D_DATAIN_SIZE_0_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DATAIN_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_RESET_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_READ_MASK            (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_RANGE                         (12:0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_WOFFSET                        (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_RANGE                       (28:16)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_WOFFSET                       (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DATAIN_SIZE_1_0
+#define CDMA_D_DATAIN_SIZE_1_0                          (_MK_ADDR_CONST(0x5020))
+#define CDMA_D_DATAIN_SIZE_1_0_SECURE                                      (0x0)
+#define CDMA_D_DATAIN_SIZE_1_0_DUAL                                        (0x0)
+#define CDMA_D_DATAIN_SIZE_1_0_SCR                                           (0)
+#define CDMA_D_DATAIN_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DATAIN_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_RANGE                       (12:0)
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_WOFFSET                      (0x0)
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DATAIN_SIZE_EXT_0_0
+#define CDMA_D_DATAIN_SIZE_EXT_0_0                      (_MK_ADDR_CONST(0x5024))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SECURE                                  (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DUAL                                    (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SCR                                       (0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_WORD_COUNT                              (0x1)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_RESET_MASK       (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_READ_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_RANGE                 (12:0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_WOFFSET                (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_RANGE               (28:16)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_WOFFSET               (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PIXEL_OFFSET_0
+#define CDMA_D_PIXEL_OFFSET_0                           (_MK_ADDR_CONST(0x5028))
+#define CDMA_D_PIXEL_OFFSET_0_SECURE                                       (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_DUAL                                         (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_SCR                                            (0)
+#define CDMA_D_PIXEL_OFFSET_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_PIXEL_OFFSET_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_RESET_MASK               (_MK_MASK_CONST(0x7001f))
+#define CDMA_D_PIXEL_OFFSET_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_READ_MASK                (_MK_MASK_CONST(0x7001f))
+#define CDMA_D_PIXEL_OFFSET_0_WRITE_MASK               (_MK_MASK_CONST(0x7001f))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_RANGE                         (4:0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_WOFFSET                       (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_RANGE                       (18:16)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_WOFFSET                       (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_RAM_TYPE_0
+#define CDMA_D_DAIN_RAM_TYPE_0                          (_MK_ADDR_CONST(0x502c))
+#define CDMA_D_DAIN_RAM_TYPE_0_SECURE                                      (0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DUAL                                        (0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_SCR                                           (0)
+#define CDMA_D_DAIN_RAM_TYPE_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DAIN_RAM_TYPE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_RANGE                       (0:0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_WOFFSET                     (0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_INIT_ENUM                  (CVIF)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF          (_MK_ENUM_CONST(0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF          (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_DAIN_ADDR_HIGH_0_0
+#define CDMA_D_DAIN_ADDR_HIGH_0_0                       (_MK_ADDR_CONST(0x5030))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SECURE                                   (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DUAL                                     (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SCR                                        (0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_WORD_COUNT                               (0x1)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_RANGE                (31:0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_WOFFSET               (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_ADDR_LOW_0_0
+#define CDMA_D_DAIN_ADDR_LOW_0_0                        (_MK_ADDR_CONST(0x5034))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SECURE                                    (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DUAL                                      (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SCR                                         (0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_WORD_COUNT                                (0x1)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT    (_MK_SHIFT_CONST(5))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_RANGE                  (31:5)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_WOFFSET                 (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_ADDR_HIGH_1_0
+#define CDMA_D_DAIN_ADDR_HIGH_1_0                       (_MK_ADDR_CONST(0x5038))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SECURE                                   (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DUAL                                     (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SCR                                        (0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_WORD_COUNT                               (0x1)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_RANGE                (31:0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_WOFFSET               (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_ADDR_LOW_1_0
+#define CDMA_D_DAIN_ADDR_LOW_1_0                        (_MK_ADDR_CONST(0x503c))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SECURE                                    (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DUAL                                      (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SCR                                         (0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_WORD_COUNT                                (0x1)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT    (_MK_SHIFT_CONST(5))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_RANGE                  (31:5)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_WOFFSET                 (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_LINE_STRIDE_0
+#define CDMA_D_LINE_STRIDE_0                            (_MK_ADDR_CONST(0x5040))
+#define CDMA_D_LINE_STRIDE_0_SECURE                                        (0x0)
+#define CDMA_D_LINE_STRIDE_0_DUAL                                          (0x0)
+#define CDMA_D_LINE_STRIDE_0_SCR                                             (0)
+#define CDMA_D_LINE_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_LINE_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_RESET_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_READ_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_STRIDE_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_RANGE                            (31:5)
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_WOFFSET                           (0x0)
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_LINE_UV_STRIDE_0
+#define CDMA_D_LINE_UV_STRIDE_0                         (_MK_ADDR_CONST(0x5044))
+#define CDMA_D_LINE_UV_STRIDE_0_SECURE                                     (0x0)
+#define CDMA_D_LINE_UV_STRIDE_0_DUAL                                       (0x0)
+#define CDMA_D_LINE_UV_STRIDE_0_SCR                                          (0)
+#define CDMA_D_LINE_UV_STRIDE_0_WORD_COUNT                                 (0x1)
+#define CDMA_D_LINE_UV_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_UV_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_UV_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT        (_MK_SHIFT_CONST(5))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_RANGE                      (31:5)
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_WOFFSET                     (0x0)
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_SURF_STRIDE_0
+#define CDMA_D_SURF_STRIDE_0                            (_MK_ADDR_CONST(0x5048))
+#define CDMA_D_SURF_STRIDE_0_SECURE                                        (0x0)
+#define CDMA_D_SURF_STRIDE_0_DUAL                                          (0x0)
+#define CDMA_D_SURF_STRIDE_0_SCR                                             (0)
+#define CDMA_D_SURF_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_SURF_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_RESET_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_SURF_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_READ_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_SURF_STRIDE_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_RANGE                            (31:5)
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_WOFFSET                           (0x0)
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_MAP_0
+#define CDMA_D_DAIN_MAP_0                               (_MK_ADDR_CONST(0x504c))
+#define CDMA_D_DAIN_MAP_0_SECURE                                           (0x0)
+#define CDMA_D_DAIN_MAP_0_DUAL                                             (0x0)
+#define CDMA_D_DAIN_MAP_0_SCR                                                (0)
+#define CDMA_D_DAIN_MAP_0_WORD_COUNT                                       (0x1)
+#define CDMA_D_DAIN_MAP_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_RESET_MASK                   (_MK_MASK_CONST(0x10001))
+#define CDMA_D_DAIN_MAP_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_READ_MASK                    (_MK_MASK_CONST(0x10001))
+#define CDMA_D_DAIN_MAP_0_WRITE_MASK                   (_MK_MASK_CONST(0x10001))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_RANGE                                (0:0)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_WOFFSET                              (0x0)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_INIT_ENUM                          (FALSE)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE                  (_MK_ENUM_CONST(0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE                   (_MK_ENUM_CONST(1))
+
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT                (_MK_SHIFT_CONST(16))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_RANGE                              (16:16)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_WOFFSET                              (0x0)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_INIT_ENUM                          (FALSE)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE                  (_MK_ENUM_CONST(0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE                   (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_RESERVED_X_CFG_0
+#define CDMA_D_RESERVED_X_CFG_0                         (_MK_ADDR_CONST(0x5050))
+#define CDMA_D_RESERVED_X_CFG_0_SECURE                                     (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_DUAL                                       (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_SCR                                          (0)
+#define CDMA_D_RESERVED_X_CFG_0_WORD_COUNT                                 (0x1)
+#define CDMA_D_RESERVED_X_CFG_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RESET_MASK           (_MK_MASK_CONST(0x3ff03ff))
+#define CDMA_D_RESERVED_X_CFG_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_READ_MASK            (_MK_MASK_CONST(0x3ff03ff))
+#define CDMA_D_RESERVED_X_CFG_0_WRITE_MASK           (_MK_MASK_CONST(0x3ff03ff))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD \
+	(_MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_RANGE                         (9:0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_WOFFSET                       (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT      (_MK_SHIFT_CONST(16))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_RANGE                    (25:16)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_WOFFSET                    (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_RESERVED_Y_CFG_0
+#define CDMA_D_RESERVED_Y_CFG_0                         (_MK_ADDR_CONST(0x5054))
+#define CDMA_D_RESERVED_Y_CFG_0_SECURE                                     (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_DUAL                                       (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_SCR                                          (0)
+#define CDMA_D_RESERVED_Y_CFG_0_WORD_COUNT                                 (0x1)
+#define CDMA_D_RESERVED_Y_CFG_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RESET_MASK            (_MK_MASK_CONST(0x1f0007))
+#define CDMA_D_RESERVED_Y_CFG_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_READ_MASK             (_MK_MASK_CONST(0x1f0007))
+#define CDMA_D_RESERVED_Y_CFG_0_WRITE_MASK            (_MK_MASK_CONST(0x1f0007))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT            (_MK_SHIFT_CONST(0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_RANGE                           (2:0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_WOFFSET                         (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT          (_MK_SHIFT_CONST(16))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_RANGE                        (20:16)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_WOFFSET                        (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_BATCH_NUMBER_0
+#define CDMA_D_BATCH_NUMBER_0                           (_MK_ADDR_CONST(0x5058))
+#define CDMA_D_BATCH_NUMBER_0_SECURE                                       (0x0)
+#define CDMA_D_BATCH_NUMBER_0_DUAL                                         (0x0)
+#define CDMA_D_BATCH_NUMBER_0_SCR                                            (0)
+#define CDMA_D_BATCH_NUMBER_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_BATCH_NUMBER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_RANGE                                (4:0)
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_WOFFSET                              (0x0)
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_BATCH_STRIDE_0
+#define CDMA_D_BATCH_STRIDE_0                           (_MK_ADDR_CONST(0x505c))
+#define CDMA_D_BATCH_STRIDE_0_SECURE                                       (0x0)
+#define CDMA_D_BATCH_STRIDE_0_DUAL                                         (0x0)
+#define CDMA_D_BATCH_STRIDE_0_SCR                                            (0)
+#define CDMA_D_BATCH_STRIDE_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_BATCH_STRIDE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_BATCH_STRIDE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_BATCH_STRIDE_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_RANGE                          (31:5)
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_WOFFSET                         (0x0)
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_ENTRY_PER_SLICE_0
+#define CDMA_D_ENTRY_PER_SLICE_0                        (_MK_ADDR_CONST(0x5060))
+#define CDMA_D_ENTRY_PER_SLICE_0_SECURE                                    (0x0)
+#define CDMA_D_ENTRY_PER_SLICE_0_DUAL                                      (0x0)
+#define CDMA_D_ENTRY_PER_SLICE_0_SCR                                         (0)
+#define CDMA_D_ENTRY_PER_SLICE_0_WORD_COUNT                                (0x1)
+#define CDMA_D_ENTRY_PER_SLICE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_RESET_MASK              (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_READ_MASK               (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_WRITE_MASK              (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD \
+	(_MK_FIELD_CONST(0xfff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_RANGE                            (11:0)
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_WOFFSET                           (0x0)
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT_MASK    (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_FETCH_GRAIN_0
+#define CDMA_D_FETCH_GRAIN_0                            (_MK_ADDR_CONST(0x5064))
+#define CDMA_D_FETCH_GRAIN_0_SECURE                                        (0x0)
+#define CDMA_D_FETCH_GRAIN_0_DUAL                                          (0x0)
+#define CDMA_D_FETCH_GRAIN_0_SCR                                             (0)
+#define CDMA_D_FETCH_GRAIN_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_FETCH_GRAIN_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_RESET_MASK                  (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_READ_MASK                   (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_WRITE_MASK                  (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD \
+	(_MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_RANGE                                 (11:0)
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_WOFFSET                                (0x0)
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_DEFAULT_MASK         (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_FORMAT_0
+#define CDMA_D_WEIGHT_FORMAT_0                          (_MK_ADDR_CONST(0x5068))
+#define CDMA_D_WEIGHT_FORMAT_0_SECURE                                      (0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_DUAL                                        (0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_SCR                                           (0)
+#define CDMA_D_WEIGHT_FORMAT_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WEIGHT_FORMAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_RANGE                         (0:0)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_WOFFSET                       (0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_INIT_ENUM            (UNCOMPRESSED)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED    (_MK_ENUM_CONST(0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED      (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_WEIGHT_SIZE_0_0
+#define CDMA_D_WEIGHT_SIZE_0_0                          (_MK_ADDR_CONST(0x506c))
+#define CDMA_D_WEIGHT_SIZE_0_0_SECURE                                      (0x0)
+#define CDMA_D_WEIGHT_SIZE_0_0_DUAL                                        (0x0)
+#define CDMA_D_WEIGHT_SIZE_0_0_SCR                                           (0)
+#define CDMA_D_WEIGHT_SIZE_0_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WEIGHT_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_RESET_MASK              (_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_READ_MASK               (_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_WRITE_MASK              (_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD \
+	(_MK_FIELD_CONST(0x3ffff, \
+	CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_RANGE                      (17:0)
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_WOFFSET                     (0x0)
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_SIZE_1_0
+#define CDMA_D_WEIGHT_SIZE_1_0                          (_MK_ADDR_CONST(0x5070))
+#define CDMA_D_WEIGHT_SIZE_1_0_SECURE                                      (0x0)
+#define CDMA_D_WEIGHT_SIZE_1_0_DUAL                                        (0x0)
+#define CDMA_D_WEIGHT_SIZE_1_0_SCR                                           (0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WEIGHT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_RANGE                        (12:0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_WOFFSET                       (0x0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_RAM_TYPE_0
+#define CDMA_D_WEIGHT_RAM_TYPE_0                        (_MK_ADDR_CONST(0x5074))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SECURE                                    (0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_DUAL                                      (0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SCR                                         (0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WORD_COUNT                                (0x1)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT      (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_RANGE                     (0:0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_WOFFSET                   (0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_INIT_ENUM                (CVIF)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF        (_MK_ENUM_CONST(0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF        (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_WEIGHT_ADDR_HIGH_0
+#define CDMA_D_WEIGHT_ADDR_HIGH_0                       (_MK_ADDR_CONST(0x5078))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SECURE                                   (0x0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_DUAL                                     (0x0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SCR                                        (0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WORD_COUNT                               (0x1)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT    (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_RANGE                  (31:0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_WOFFSET                 (0x0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_ADDR_LOW_0
+#define CDMA_D_WEIGHT_ADDR_LOW_0                        (_MK_ADDR_CONST(0x507c))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SECURE                                    (0x0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_DUAL                                      (0x0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SCR                                         (0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WORD_COUNT                                (0x1)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT      (_MK_SHIFT_CONST(5))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_RANGE                    (31:5)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_WOFFSET                   (0x0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_BYTES_0
+#define CDMA_D_WEIGHT_BYTES_0                           (_MK_ADDR_CONST(0x5080))
+#define CDMA_D_WEIGHT_BYTES_0_SECURE                                       (0x0)
+#define CDMA_D_WEIGHT_BYTES_0_DUAL                                         (0x0)
+#define CDMA_D_WEIGHT_BYTES_0_SCR                                            (0)
+#define CDMA_D_WEIGHT_BYTES_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_WEIGHT_BYTES_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_RESET_MASK            (_MK_MASK_CONST(0xffffff80))
+#define CDMA_D_WEIGHT_BYTES_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_READ_MASK             (_MK_MASK_CONST(0xffffff80))
+#define CDMA_D_WEIGHT_BYTES_0_WRITE_MASK            (_MK_MASK_CONST(0xffffff80))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT            (_MK_SHIFT_CONST(7))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1ffffff, \
+	CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_RANGE                          (31:7)
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_WOFFSET                         (0x0)
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffffff))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WGS_ADDR_HIGH_0
+#define CDMA_D_WGS_ADDR_HIGH_0                          (_MK_ADDR_CONST(0x5084))
+#define CDMA_D_WGS_ADDR_HIGH_0_SECURE                                      (0x0)
+#define CDMA_D_WGS_ADDR_HIGH_0_DUAL                                        (0x0)
+#define CDMA_D_WGS_ADDR_HIGH_0_SCR                                           (0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WGS_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_RANGE                        (31:0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_WOFFSET                       (0x0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WGS_ADDR_LOW_0
+#define CDMA_D_WGS_ADDR_LOW_0                           (_MK_ADDR_CONST(0x5088))
+#define CDMA_D_WGS_ADDR_LOW_0_SECURE                                       (0x0)
+#define CDMA_D_WGS_ADDR_LOW_0_DUAL                                         (0x0)
+#define CDMA_D_WGS_ADDR_LOW_0_SCR                                            (0)
+#define CDMA_D_WGS_ADDR_LOW_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_WGS_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WGS_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WGS_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_RANGE                          (31:5)
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_WOFFSET                         (0x0)
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WMB_ADDR_HIGH_0
+#define CDMA_D_WMB_ADDR_HIGH_0                          (_MK_ADDR_CONST(0x508c))
+#define CDMA_D_WMB_ADDR_HIGH_0_SECURE                                      (0x0)
+#define CDMA_D_WMB_ADDR_HIGH_0_DUAL                                        (0x0)
+#define CDMA_D_WMB_ADDR_HIGH_0_SCR                                           (0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WMB_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_RANGE                        (31:0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_WOFFSET                       (0x0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WMB_ADDR_LOW_0
+#define CDMA_D_WMB_ADDR_LOW_0                           (_MK_ADDR_CONST(0x5090))
+#define CDMA_D_WMB_ADDR_LOW_0_SECURE                                       (0x0)
+#define CDMA_D_WMB_ADDR_LOW_0_DUAL                                         (0x0)
+#define CDMA_D_WMB_ADDR_LOW_0_SCR                                            (0)
+#define CDMA_D_WMB_ADDR_LOW_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_WMB_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WMB_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WMB_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_RANGE                          (31:5)
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_WOFFSET                         (0x0)
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WMB_BYTES_0
+#define CDMA_D_WMB_BYTES_0                              (_MK_ADDR_CONST(0x5094))
+#define CDMA_D_WMB_BYTES_0_SECURE                                          (0x0)
+#define CDMA_D_WMB_BYTES_0_DUAL                                            (0x0)
+#define CDMA_D_WMB_BYTES_0_SCR                                               (0)
+#define CDMA_D_WMB_BYTES_0_WORD_COUNT                                      (0x1)
+#define CDMA_D_WMB_BYTES_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_RESET_MASK                (_MK_MASK_CONST(0xfffff80))
+#define CDMA_D_WMB_BYTES_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_READ_MASK                 (_MK_MASK_CONST(0xfffff80))
+#define CDMA_D_WMB_BYTES_0_WRITE_MASK                (_MK_MASK_CONST(0xfffff80))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT                  (_MK_SHIFT_CONST(7))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1fffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_RANGE                                (27:7)
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_WOFFSET                               (0x0)
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_DEFAULT_MASK     (_MK_MASK_CONST(0x1fffff))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_MEAN_FORMAT_0
+#define CDMA_D_MEAN_FORMAT_0                            (_MK_ADDR_CONST(0x5098))
+#define CDMA_D_MEAN_FORMAT_0_SECURE                                        (0x0)
+#define CDMA_D_MEAN_FORMAT_0_DUAL                                          (0x0)
+#define CDMA_D_MEAN_FORMAT_0_SCR                                             (0)
+#define CDMA_D_MEAN_FORMAT_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_MEAN_FORMAT_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_RANGE                             (0:0)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_WOFFSET                           (0x0)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_INIT_ENUM                     (DISABLE)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE             (_MK_ENUM_CONST(0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE              (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_MEAN_GLOBAL_0_0
+#define CDMA_D_MEAN_GLOBAL_0_0                          (_MK_ADDR_CONST(0x509c))
+#define CDMA_D_MEAN_GLOBAL_0_0_SECURE                                      (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_DUAL                                        (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_SCR                                           (0)
+#define CDMA_D_MEAN_GLOBAL_0_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_MEAN_GLOBAL_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_RANGE                              (15:0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT               (_MK_SHIFT_CONST(16))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_RANGE                             (31:16)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_MEAN_GLOBAL_1_0
+#define CDMA_D_MEAN_GLOBAL_1_0                          (_MK_ADDR_CONST(0x50a0))
+#define CDMA_D_MEAN_GLOBAL_1_0_SECURE                                      (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_DUAL                                        (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_SCR                                           (0)
+#define CDMA_D_MEAN_GLOBAL_1_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_MEAN_GLOBAL_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_RANGE                              (15:0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT               (_MK_SHIFT_CONST(16))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_RANGE                             (31:16)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CVT_CFG_0
+#define CDMA_D_CVT_CFG_0                                (_MK_ADDR_CONST(0x50a4))
+#define CDMA_D_CVT_CFG_0_SECURE                                            (0x0)
+#define CDMA_D_CVT_CFG_0_DUAL                                              (0x0)
+#define CDMA_D_CVT_CFG_0_SCR                                                 (0)
+#define CDMA_D_CVT_CFG_0_WORD_COUNT                                        (0x1)
+#define CDMA_D_CVT_CFG_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x3f1))
+#define CDMA_D_CVT_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x3f1))
+#define CDMA_D_CVT_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x3f1))
+#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT))
+#define CDMA_D_CVT_CFG_0_CVT_EN_RANGE                                      (0:0)
+#define CDMA_D_CVT_CFG_0_CVT_EN_WOFFSET                                    (0x0)
+#define CDMA_D_CVT_CFG_0_CVT_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define CDMA_D_CVT_CFG_0_CVT_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CDMA_D_CVT_CFG_0_CVT_EN_INIT_ENUM                              (DISABLE)
+#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT                 (_MK_SHIFT_CONST(4))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_RANGE                                (9:4)
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_WOFFSET                              (0x0)
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_DEFAULT_MASK        (_MK_MASK_CONST(0x3f))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CVT_OFFSET_0
+#define CDMA_D_CVT_OFFSET_0                             (_MK_ADDR_CONST(0x50a8))
+#define CDMA_D_CVT_OFFSET_0_SECURE                                         (0x0)
+#define CDMA_D_CVT_OFFSET_0_DUAL                                           (0x0)
+#define CDMA_D_CVT_OFFSET_0_SCR                                              (0)
+#define CDMA_D_CVT_OFFSET_0_WORD_COUNT                                     (0x1)
+#define CDMA_D_CVT_OFFSET_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_RESET_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_READ_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_WRITE_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_RANGE                              (15:0)
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_WOFFSET                             (0x0)
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CVT_SCALE_0
+#define CDMA_D_CVT_SCALE_0                              (_MK_ADDR_CONST(0x50ac))
+#define CDMA_D_CVT_SCALE_0_SECURE                                          (0x0)
+#define CDMA_D_CVT_SCALE_0_DUAL                                            (0x0)
+#define CDMA_D_CVT_SCALE_0_SCR                                               (0)
+#define CDMA_D_CVT_SCALE_0_WORD_COUNT                                      (0x1)
+#define CDMA_D_CVT_SCALE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_RESET_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_READ_MASK                    (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_WRITE_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_RANGE                                (15:0)
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_WOFFSET                               (0x0)
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_DEFAULT_MASK       (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CONV_STRIDE_0
+#define CDMA_D_CONV_STRIDE_0                            (_MK_ADDR_CONST(0x50b0))
+#define CDMA_D_CONV_STRIDE_0_SECURE                                        (0x0)
+#define CDMA_D_CONV_STRIDE_0_DUAL                                          (0x0)
+#define CDMA_D_CONV_STRIDE_0_SCR                                             (0)
+#define CDMA_D_CONV_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_CONV_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_RESET_MASK                (_MK_MASK_CONST(0x70007))
+#define CDMA_D_CONV_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_READ_MASK                 (_MK_MASK_CONST(0x70007))
+#define CDMA_D_CONV_STRIDE_0_WRITE_MASK                (_MK_MASK_CONST(0x70007))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT            (_MK_SHIFT_CONST(0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_RANGE                           (2:0)
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_WOFFSET                         (0x0)
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT           (_MK_SHIFT_CONST(16))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_RANGE                         (18:16)
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_WOFFSET                         (0x0)
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_ZERO_PADDING_0
+#define CDMA_D_ZERO_PADDING_0                           (_MK_ADDR_CONST(0x50b4))
+#define CDMA_D_ZERO_PADDING_0_SECURE                                       (0x0)
+#define CDMA_D_ZERO_PADDING_0_DUAL                                         (0x0)
+#define CDMA_D_ZERO_PADDING_0_SCR                                            (0)
+#define CDMA_D_ZERO_PADDING_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_ZERO_PADDING_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_RESET_MASK            (_MK_MASK_CONST(0x3f1f3f1f))
+#define CDMA_D_ZERO_PADDING_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_READ_MASK             (_MK_MASK_CONST(0x3f1f3f1f))
+#define CDMA_D_ZERO_PADDING_0_WRITE_MASK            (_MK_MASK_CONST(0x3f1f3f1f))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_RANGE                               (4:0)
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_WOFFSET                             (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT_MASK       (_MK_MASK_CONST(0x1f))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT               (_MK_SHIFT_CONST(8))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_RANGE                             (13:8)
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_WOFFSET                            (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_DEFAULT_MASK      (_MK_MASK_CONST(0x3f))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT                (_MK_SHIFT_CONST(16))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_RANGE                              (20:16)
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_WOFFSET                              (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT             (_MK_SHIFT_CONST(24))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_RANGE                           (29:24)
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_WOFFSET                           (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_DEFAULT_MASK     (_MK_MASK_CONST(0x3f))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_ZERO_PADDING_VALUE_0
+#define CDMA_D_ZERO_PADDING_VALUE_0                     (_MK_ADDR_CONST(0x50b8))
+#define CDMA_D_ZERO_PADDING_VALUE_0_SECURE                                 (0x0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_DUAL                                   (0x0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_SCR                                      (0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_WORD_COUNT                             (0x1)
+#define CDMA_D_ZERO_PADDING_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_RANGE                       (15:0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_WOFFSET                      (0x0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_BANK_0
+#define CDMA_D_BANK_0                                   (_MK_ADDR_CONST(0x50bc))
+#define CDMA_D_BANK_0_SECURE                                               (0x0)
+#define CDMA_D_BANK_0_DUAL                                                 (0x0)
+#define CDMA_D_BANK_0_SCR                                                    (0)
+#define CDMA_D_BANK_0_WORD_COUNT                                           (0x1)
+#define CDMA_D_BANK_0_RESET_VAL                            (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_RESET_MASK                       (_MK_MASK_CONST(0xf000f))
+#define CDMA_D_BANK_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_READ_MASK                        (_MK_MASK_CONST(0xf000f))
+#define CDMA_D_BANK_0_WRITE_MASK                       (_MK_MASK_CONST(0xf000f))
+#define CDMA_D_BANK_0_DATA_BANK_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CDMA_D_BANK_0_DATA_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_D_BANK_0_DATA_BANK_SHIFT))
+#define CDMA_D_BANK_0_DATA_BANK_RANGE                                      (3:0)
+#define CDMA_D_BANK_0_DATA_BANK_WOFFSET                                    (0x0)
+#define CDMA_D_BANK_0_DATA_BANK_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_DEFAULT_MASK               (_MK_MASK_CONST(0xf))
+#define CDMA_D_BANK_0_DATA_BANK_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+
+#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT                    (_MK_SHIFT_CONST(16))
+#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT))
+#define CDMA_D_BANK_0_WEIGHT_BANK_RANGE                                  (19:16)
+#define CDMA_D_BANK_0_WEIGHT_BANK_WOFFSET                                  (0x0)
+#define CDMA_D_BANK_0_WEIGHT_BANK_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_DEFAULT_MASK             (_MK_MASK_CONST(0xf))
+#define CDMA_D_BANK_0_WEIGHT_BANK_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_NAN_FLUSH_TO_ZERO_0
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0                      (_MK_ADDR_CONST(0x50c0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SECURE                                  (0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_DUAL                                    (0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SCR                                       (0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                              (0x1)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_READ_MASK               (_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                       (0:0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                     (0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM               (DISABLE)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE       (_MK_ENUM_CONST(0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE        (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_NAN_INPUT_DATA_NUM_0
+#define CDMA_D_NAN_INPUT_DATA_NUM_0                     (_MK_ADDR_CONST(0x50c4))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SECURE                                 (0x0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_DUAL                                   (0x0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SCR                                      (0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_WORD_COUNT                             (0x1)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT      (_MK_SHIFT_CONST(0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_RANGE                    (31:0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_WOFFSET                   (0x0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0                   (_MK_ADDR_CONST(0x50c8))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SECURE                               (0x0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_DUAL                                 (0x0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SCR                                    (0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_WORD_COUNT                           (0x1)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_RANGE                (31:0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_WOFFSET               (0x0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_INF_INPUT_DATA_NUM_0
+#define CDMA_D_INF_INPUT_DATA_NUM_0                     (_MK_ADDR_CONST(0x50cc))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SECURE                                 (0x0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_DUAL                                   (0x0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SCR                                      (0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_WORD_COUNT                             (0x1)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT      (_MK_SHIFT_CONST(0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_RANGE                    (31:0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_WOFFSET                   (0x0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0                   (_MK_ADDR_CONST(0x50d0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SECURE                               (0x0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_DUAL                                 (0x0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SCR                                    (0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_WORD_COUNT                           (0x1)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_RANGE                (31:0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_WOFFSET               (0x0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_ENABLE_0
+#define CDMA_D_PERF_ENABLE_0                            (_MK_ADDR_CONST(0x50d4))
+#define CDMA_D_PERF_ENABLE_0_SECURE                                        (0x0)
+#define CDMA_D_PERF_ENABLE_0_DUAL                                          (0x0)
+#define CDMA_D_PERF_ENABLE_0_SCR                                             (0)
+#define CDMA_D_PERF_ENABLE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_PERF_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                                  (0:0)
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                (0x0)
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_DAT_READ_STALL_0
+#define CDMA_D_PERF_DAT_READ_STALL_0                    (_MK_ADDR_CONST(0x50d8))
+#define CDMA_D_PERF_DAT_READ_STALL_0_SECURE                                (0x0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DUAL                                  (0x0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_SCR                                     (0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_WORD_COUNT                            (0x1)
+#define CDMA_D_PERF_DAT_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT     (_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_RANGE                   (31:0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_WOFFSET                  (0x0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_WT_READ_STALL_0
+#define CDMA_D_PERF_WT_READ_STALL_0                     (_MK_ADDR_CONST(0x50dc))
+#define CDMA_D_PERF_WT_READ_STALL_0_SECURE                                 (0x0)
+#define CDMA_D_PERF_WT_READ_STALL_0_DUAL                                   (0x0)
+#define CDMA_D_PERF_WT_READ_STALL_0_SCR                                      (0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WORD_COUNT                             (0x1)
+#define CDMA_D_PERF_WT_READ_STALL_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_STALL_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_STALL_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_RANGE                     (31:0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_WOFFSET                    (0x0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_DAT_READ_LATENCY_0
+#define CDMA_D_PERF_DAT_READ_LATENCY_0                  (_MK_ADDR_CONST(0x50e0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SECURE                              (0x0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DUAL                                (0x0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SCR                                   (0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_WORD_COUNT                          (0x1)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_RANGE               (31:0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_WOFFSET              (0x0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_WT_READ_LATENCY_0
+#define CDMA_D_PERF_WT_READ_LATENCY_0                   (_MK_ADDR_CONST(0x50e4))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SECURE                               (0x0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_DUAL                                 (0x0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SCR                                    (0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WORD_COUNT                           (0x1)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_RANGE                 (31:0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_WOFFSET                (0x0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CYA_0
+#define CDMA_D_CYA_0                                    (_MK_ADDR_CONST(0x50e8))
+#define CDMA_D_CYA_0_SECURE                                                (0x0)
+#define CDMA_D_CYA_0_DUAL                                                  (0x0)
+#define CDMA_D_CYA_0_SCR                                                     (0)
+#define CDMA_D_CYA_0_WORD_COUNT                                            (0x1)
+#define CDMA_D_CYA_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_RESET_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_READ_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_WRITE_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_CYA_SHIFT                              (_MK_SHIFT_CONST(0))
+#define CDMA_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT))
+#define CDMA_D_CYA_0_CYA_RANGE                                            (31:0)
+#define CDMA_D_CYA_0_CYA_WOFFSET                                           (0x0)
+#define CDMA_D_CYA_0_CYA_DEFAULT                           (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_CYA_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_S_STATUS_0
+#define CSC_S_STATUS_0                                  (_MK_ADDR_CONST(0x6000))
+#define CSC_S_STATUS_0_SECURE                                              (0x0)
+#define CSC_S_STATUS_0_DUAL                                                (0x0)
+#define CSC_S_STATUS_0_SCR                                                   (0)
+#define CSC_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define CSC_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define CSC_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define CSC_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CSC_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT))
+#define CSC_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define CSC_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define CSC_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define CSC_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CSC_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define CSC_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define CSC_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define CSC_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define CSC_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define CSC_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT))
+#define CSC_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define CSC_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define CSC_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define CSC_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CSC_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define CSC_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define CSC_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define CSC_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register CSC_S_POINTER_0
+#define CSC_S_POINTER_0                                 (_MK_ADDR_CONST(0x6004))
+#define CSC_S_POINTER_0_SECURE                                             (0x0)
+#define CSC_S_POINTER_0_DUAL                                               (0x0)
+#define CSC_S_POINTER_0_SCR                                                  (0)
+#define CSC_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define CSC_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define CSC_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define CSC_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CSC_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT))
+#define CSC_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define CSC_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define CSC_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define CSC_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define CSC_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define CSC_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CSC_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT))
+#define CSC_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define CSC_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define CSC_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define CSC_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define CSC_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_OP_ENABLE_0
+#define CSC_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0x6008))
+#define CSC_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define CSC_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define CSC_D_OP_ENABLE_0_SCR                                                (0)
+#define CSC_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define CSC_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CSC_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CSC_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define CSC_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define CSC_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_MISC_CFG_0
+#define CSC_D_MISC_CFG_0                                (_MK_ADDR_CONST(0x600c))
+#define CSC_D_MISC_CFG_0_SECURE                                            (0x0)
+#define CSC_D_MISC_CFG_0_DUAL                                              (0x0)
+#define CSC_D_MISC_CFG_0_SCR                                                 (0)
+#define CSC_D_MISC_CFG_0_WORD_COUNT                                        (0x1)
+#define CSC_D_MISC_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x1100))
+#define CSC_D_MISC_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x11113301))
+#define CSC_D_MISC_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x11113301))
+#define CSC_D_MISC_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x11113301))
+#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CSC_D_MISC_CFG_0_CONV_MODE_RANGE                                   (0:0)
+#define CSC_D_MISC_CFG_0_CONV_MODE_WOFFSET                                 (0x0)
+#define CSC_D_MISC_CFG_0_CONV_MODE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                            (DIRECT)
+#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT                    (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                  (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT                 (_MK_SHIFT_CONST(8))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_RANGE                                (9:8)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_WOFFSET                              (0x0)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_DEFAULT              (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                          (INT16)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8                   (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16                  (_MK_ENUM_CONST(1))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16                   (_MK_ENUM_CONST(2))
+
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT              (_MK_SHIFT_CONST(12))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_RANGE                            (13:12)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                            (0x0)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT            (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK       (_MK_MASK_CONST(0x3))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                        (INT16)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8                 (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16                (_MK_ENUM_CONST(1))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16                 (_MK_ENUM_CONST(2))
+
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT                  (_MK_SHIFT_CONST(16))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_RANGE                                (16:16)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_WOFFSET                                (0x0)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_INIT_ENUM                          (DISABLE)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE                  (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE                   (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT                (_MK_SHIFT_CONST(20))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_RANGE                              (20:20)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_WOFFSET                              (0x0)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_INIT_ENUM                        (DISABLE)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE                (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                 (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT               (_MK_SHIFT_CONST(24))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_RANGE                             (24:24)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_WOFFSET                             (0x0)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_INIT_ENUM                       (DISABLE)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE               (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE                (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT             (_MK_SHIFT_CONST(28))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_RANGE                           (28:28)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_WOFFSET                           (0x0)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_INIT_ENUM                     (DISABLE)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE             (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE              (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_DATAIN_FORMAT_0
+#define CSC_D_DATAIN_FORMAT_0                           (_MK_ADDR_CONST(0x6010))
+#define CSC_D_DATAIN_FORMAT_0_SECURE                                       (0x0)
+#define CSC_D_DATAIN_FORMAT_0_DUAL                                         (0x0)
+#define CSC_D_DATAIN_FORMAT_0_SCR                                            (0)
+#define CSC_D_DATAIN_FORMAT_0_WORD_COUNT                                   (0x1)
+#define CSC_D_DATAIN_FORMAT_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_READ_MASK                    (_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT           (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_RANGE                          (0:0)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_WOFFSET                        (0x0)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_INIT_ENUM                  (FEATURE)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE          (_MK_ENUM_CONST(0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL            (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_DATAIN_SIZE_EXT_0_0
+#define CSC_D_DATAIN_SIZE_EXT_0_0                       (_MK_ADDR_CONST(0x6014))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SECURE                                   (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DUAL                                     (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SCR                                        (0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_WORD_COUNT                               (0x1)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_RESET_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_READ_MASK         (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT    (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_RANGE                  (12:0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_WOFFSET                 (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_RANGE                (28:16)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_WOFFSET                (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DATAIN_SIZE_EXT_1_0
+#define CSC_D_DATAIN_SIZE_EXT_1_0                       (_MK_ADDR_CONST(0x6018))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SECURE                                   (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DUAL                                     (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SCR                                        (0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_WORD_COUNT                               (0x1)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_RESET_MASK            (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_READ_MASK             (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_RANGE                (12:0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_WOFFSET               (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_BATCH_NUMBER_0
+#define CSC_D_BATCH_NUMBER_0                            (_MK_ADDR_CONST(0x601c))
+#define CSC_D_BATCH_NUMBER_0_SECURE                                        (0x0)
+#define CSC_D_BATCH_NUMBER_0_DUAL                                          (0x0)
+#define CSC_D_BATCH_NUMBER_0_SCR                                             (0)
+#define CSC_D_BATCH_NUMBER_0_WORD_COUNT                                    (0x1)
+#define CSC_D_BATCH_NUMBER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_RESET_MASK                   (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_READ_MASK                    (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_WRITE_MASK                   (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_RANGE                                 (4:0)
+#define CSC_D_BATCH_NUMBER_0_BATCHES_WOFFSET                               (0x0)
+#define CSC_D_BATCH_NUMBER_0_BATCHES_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK         (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_POST_Y_EXTENSION_0
+#define CSC_D_POST_Y_EXTENSION_0                        (_MK_ADDR_CONST(0x6020))
+#define CSC_D_POST_Y_EXTENSION_0_SECURE                                    (0x0)
+#define CSC_D_POST_Y_EXTENSION_0_DUAL                                      (0x0)
+#define CSC_D_POST_Y_EXTENSION_0_SCR                                         (0)
+#define CSC_D_POST_Y_EXTENSION_0_WORD_COUNT                                (0x1)
+#define CSC_D_POST_Y_EXTENSION_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT          (_MK_SHIFT_CONST(0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_RANGE                         (1:0)
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_WOFFSET                       (0x0)
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ENTRY_PER_SLICE_0
+#define CSC_D_ENTRY_PER_SLICE_0                         (_MK_ADDR_CONST(0x6024))
+#define CSC_D_ENTRY_PER_SLICE_0_SECURE                                     (0x0)
+#define CSC_D_ENTRY_PER_SLICE_0_DUAL                                       (0x0)
+#define CSC_D_ENTRY_PER_SLICE_0_SCR                                          (0)
+#define CSC_D_ENTRY_PER_SLICE_0_WORD_COUNT                                 (0x1)
+#define CSC_D_ENTRY_PER_SLICE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_RESET_MASK               (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_READ_MASK                (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_WRITE_MASK               (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT               (_MK_SHIFT_CONST(0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD \
+	(_MK_FIELD_CONST(0xfff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_RANGE                             (11:0)
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_WOFFSET                            (0x0)
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT_MASK     (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WEIGHT_FORMAT_0
+#define CSC_D_WEIGHT_FORMAT_0                           (_MK_ADDR_CONST(0x6028))
+#define CSC_D_WEIGHT_FORMAT_0_SECURE                                       (0x0)
+#define CSC_D_WEIGHT_FORMAT_0_DUAL                                         (0x0)
+#define CSC_D_WEIGHT_FORMAT_0_SCR                                            (0)
+#define CSC_D_WEIGHT_FORMAT_0_WORD_COUNT                                   (0x1)
+#define CSC_D_WEIGHT_FORMAT_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_READ_MASK                    (_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT           (_MK_SHIFT_CONST(0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_RANGE                          (0:0)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_WOFFSET                        (0x0)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_INIT_ENUM             (UNCOMPRESSED)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED     (_MK_ENUM_CONST(0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED       (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_WEIGHT_SIZE_EXT_0_0
+#define CSC_D_WEIGHT_SIZE_EXT_0_0                       (_MK_ADDR_CONST(0x602c))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SECURE                                   (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_DUAL                                     (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SCR                                        (0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WORD_COUNT                               (0x1)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_RESET_MASK          (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_READ_MASK           (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WRITE_MASK          (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT    (_MK_SHIFT_CONST(0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_RANGE                   (4:0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_WOFFSET                 (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_RANGE                (20:16)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_WOFFSET                (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WEIGHT_SIZE_EXT_1_0
+#define CSC_D_WEIGHT_SIZE_EXT_1_0                       (_MK_ADDR_CONST(0x6030))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SECURE                                   (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_DUAL                                     (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SCR                                        (0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WORD_COUNT                               (0x1)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_RESET_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_READ_MASK         (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_RANGE                (12:0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_WOFFSET               (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT      (_MK_SHIFT_CONST(16))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_RANGE                    (28:16)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_WOFFSET                    (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WEIGHT_BYTES_0
+#define CSC_D_WEIGHT_BYTES_0                            (_MK_ADDR_CONST(0x6034))
+#define CSC_D_WEIGHT_BYTES_0_SECURE                                        (0x0)
+#define CSC_D_WEIGHT_BYTES_0_DUAL                                          (0x0)
+#define CSC_D_WEIGHT_BYTES_0_SCR                                             (0)
+#define CSC_D_WEIGHT_BYTES_0_WORD_COUNT                                    (0x1)
+#define CSC_D_WEIGHT_BYTES_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_RESET_MASK             (_MK_MASK_CONST(0xffffff80))
+#define CSC_D_WEIGHT_BYTES_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_READ_MASK              (_MK_MASK_CONST(0xffffff80))
+#define CSC_D_WEIGHT_BYTES_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff80))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT             (_MK_SHIFT_CONST(7))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1ffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_RANGE                           (31:7)
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_WOFFSET                          (0x0)
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffffff))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WMB_BYTES_0
+#define CSC_D_WMB_BYTES_0                               (_MK_ADDR_CONST(0x6038))
+#define CSC_D_WMB_BYTES_0_SECURE                                           (0x0)
+#define CSC_D_WMB_BYTES_0_DUAL                                             (0x0)
+#define CSC_D_WMB_BYTES_0_SCR                                                (0)
+#define CSC_D_WMB_BYTES_0_WORD_COUNT                                       (0x1)
+#define CSC_D_WMB_BYTES_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_RESET_MASK                 (_MK_MASK_CONST(0xfffff80))
+#define CSC_D_WMB_BYTES_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_READ_MASK                  (_MK_MASK_CONST(0xfffff80))
+#define CSC_D_WMB_BYTES_0_WRITE_MASK                 (_MK_MASK_CONST(0xfffff80))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT                   (_MK_SHIFT_CONST(7))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1fffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_RANGE                                 (27:7)
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_WOFFSET                                (0x0)
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_DEFAULT_MASK      (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DATAOUT_SIZE_0_0
+#define CSC_D_DATAOUT_SIZE_0_0                          (_MK_ADDR_CONST(0x603c))
+#define CSC_D_DATAOUT_SIZE_0_0_SECURE                                      (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_DUAL                                        (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_SCR                                           (0)
+#define CSC_D_DATAOUT_SIZE_0_0_WORD_COUNT                                  (0x1)
+#define CSC_D_DATAOUT_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_RESET_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_READ_MASK            (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT          (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_RANGE                        (12:0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_WOFFSET                       (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT        (_MK_SHIFT_CONST(16))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_RANGE                      (28:16)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_WOFFSET                      (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DATAOUT_SIZE_1_0
+#define CSC_D_DATAOUT_SIZE_1_0                          (_MK_ADDR_CONST(0x6040))
+#define CSC_D_DATAOUT_SIZE_1_0_SECURE                                      (0x0)
+#define CSC_D_DATAOUT_SIZE_1_0_DUAL                                        (0x0)
+#define CSC_D_DATAOUT_SIZE_1_0_SCR                                           (0)
+#define CSC_D_DATAOUT_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define CSC_D_DATAOUT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                      (12:0)
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                     (0x0)
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ATOMICS_0
+#define CSC_D_ATOMICS_0                                 (_MK_ADDR_CONST(0x6044))
+#define CSC_D_ATOMICS_0_SECURE                                             (0x0)
+#define CSC_D_ATOMICS_0_DUAL                                               (0x0)
+#define CSC_D_ATOMICS_0_SCR                                                  (0)
+#define CSC_D_ATOMICS_0_WORD_COUNT                                         (0x1)
+#define CSC_D_ATOMICS_0_RESET_VAL                          (_MK_MASK_CONST(0x1))
+#define CSC_D_ATOMICS_0_RESET_MASK                    (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_READ_MASK                     (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_WRITE_MASK                    (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_ATOMICS_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CSC_D_ATOMICS_0_ATOMICS_FIELD \
+	(_MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT))
+#define CSC_D_ATOMICS_0_ATOMICS_RANGE                                     (20:0)
+#define CSC_D_ATOMICS_0_ATOMICS_WOFFSET                                    (0x0)
+#define CSC_D_ATOMICS_0_ATOMICS_DEFAULT                    (_MK_MASK_CONST(0x1))
+#define CSC_D_ATOMICS_0_ATOMICS_DEFAULT_MASK          (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_ATOMICS_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_ATOMICS_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_ATOMICS_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_ATOMICS_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_RELEASE_0
+#define CSC_D_RELEASE_0                                 (_MK_ADDR_CONST(0x6048))
+#define CSC_D_RELEASE_0_SECURE                                             (0x0)
+#define CSC_D_RELEASE_0_DUAL                                               (0x0)
+#define CSC_D_RELEASE_0_SCR                                                  (0)
+#define CSC_D_RELEASE_0_WORD_COUNT                                         (0x1)
+#define CSC_D_RELEASE_0_RESET_VAL                          (_MK_MASK_CONST(0x1))
+#define CSC_D_RELEASE_0_RESET_MASK                       (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_READ_MASK                        (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_WRITE_MASK                       (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CSC_D_RELEASE_0_RLS_SLICES_FIELD \
+	(_MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT))
+#define CSC_D_RELEASE_0_RLS_SLICES_RANGE                                  (11:0)
+#define CSC_D_RELEASE_0_RLS_SLICES_WOFFSET                                 (0x0)
+#define CSC_D_RELEASE_0_RLS_SLICES_DEFAULT                 (_MK_MASK_CONST(0x1))
+#define CSC_D_RELEASE_0_RLS_SLICES_DEFAULT_MASK          (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_RLS_SLICES_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_RLS_SLICES_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_RLS_SLICES_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_RLS_SLICES_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_CONV_STRIDE_EXT_0
+#define CSC_D_CONV_STRIDE_EXT_0                         (_MK_ADDR_CONST(0x604c))
+#define CSC_D_CONV_STRIDE_EXT_0_SECURE                                     (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_DUAL                                       (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_SCR                                          (0)
+#define CSC_D_CONV_STRIDE_EXT_0_WORD_COUNT                                 (0x1)
+#define CSC_D_CONV_STRIDE_EXT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_RESET_MASK             (_MK_MASK_CONST(0x70007))
+#define CSC_D_CONV_STRIDE_EXT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_READ_MASK              (_MK_MASK_CONST(0x70007))
+#define CSC_D_CONV_STRIDE_EXT_0_WRITE_MASK             (_MK_MASK_CONST(0x70007))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT     (_MK_SHIFT_CONST(0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD \
+	(_MK_FIELD_CONST(0x7, \
+	CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_RANGE                    (2:0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_WOFFSET                  (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT    (_MK_SHIFT_CONST(16))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD \
+	(_MK_FIELD_CONST(0x7, \
+	CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_RANGE                  (18:16)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_WOFFSET                  (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DILATION_EXT_0
+#define CSC_D_DILATION_EXT_0                            (_MK_ADDR_CONST(0x6050))
+#define CSC_D_DILATION_EXT_0_SECURE                                        (0x0)
+#define CSC_D_DILATION_EXT_0_DUAL                                          (0x0)
+#define CSC_D_DILATION_EXT_0_SCR                                             (0)
+#define CSC_D_DILATION_EXT_0_WORD_COUNT                                    (0x1)
+#define CSC_D_DILATION_EXT_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_RESET_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_DILATION_EXT_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_READ_MASK                (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_DILATION_EXT_0_WRITE_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT           (_MK_SHIFT_CONST(0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_RANGE                          (4:0)
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_WOFFSET                        (0x0)
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT          (_MK_SHIFT_CONST(16))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_RANGE                        (20:16)
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_WOFFSET                        (0x0)
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ZERO_PADDING_0
+#define CSC_D_ZERO_PADDING_0                            (_MK_ADDR_CONST(0x6054))
+#define CSC_D_ZERO_PADDING_0_SECURE                                        (0x0)
+#define CSC_D_ZERO_PADDING_0_DUAL                                          (0x0)
+#define CSC_D_ZERO_PADDING_0_SCR                                             (0)
+#define CSC_D_ZERO_PADDING_0_WORD_COUNT                                    (0x1)
+#define CSC_D_ZERO_PADDING_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_RESET_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_ZERO_PADDING_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_READ_MASK                (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_ZERO_PADDING_0_WRITE_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_RANGE                                (4:0)
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_WOFFSET                              (0x0)
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT                 (_MK_SHIFT_CONST(16))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_RANGE                               (20:16)
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_WOFFSET                               (0x0)
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_DEFAULT_MASK         (_MK_MASK_CONST(0x1f))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ZERO_PADDING_VALUE_0
+#define CSC_D_ZERO_PADDING_VALUE_0                      (_MK_ADDR_CONST(0x6058))
+#define CSC_D_ZERO_PADDING_VALUE_0_SECURE                                  (0x0)
+#define CSC_D_ZERO_PADDING_VALUE_0_DUAL                                    (0x0)
+#define CSC_D_ZERO_PADDING_VALUE_0_SCR                                       (0)
+#define CSC_D_ZERO_PADDING_VALUE_0_WORD_COUNT                              (0x1)
+#define CSC_D_ZERO_PADDING_VALUE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_READ_MASK            (_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT          (_MK_SHIFT_CONST(0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_RANGE                        (15:0)
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_WOFFSET                       (0x0)
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_BANK_0
+#define CSC_D_BANK_0                                    (_MK_ADDR_CONST(0x605c))
+#define CSC_D_BANK_0_SECURE                                                (0x0)
+#define CSC_D_BANK_0_DUAL                                                  (0x0)
+#define CSC_D_BANK_0_SCR                                                     (0)
+#define CSC_D_BANK_0_WORD_COUNT                                            (0x1)
+#define CSC_D_BANK_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_RESET_MASK                        (_MK_MASK_CONST(0xf000f))
+#define CSC_D_BANK_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_READ_MASK                         (_MK_MASK_CONST(0xf000f))
+#define CSC_D_BANK_0_WRITE_MASK                        (_MK_MASK_CONST(0xf000f))
+#define CSC_D_BANK_0_DATA_BANK_SHIFT                        (_MK_SHIFT_CONST(0))
+#define CSC_D_BANK_0_DATA_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CSC_D_BANK_0_DATA_BANK_SHIFT))
+#define CSC_D_BANK_0_DATA_BANK_RANGE                                       (3:0)
+#define CSC_D_BANK_0_DATA_BANK_WOFFSET                                     (0x0)
+#define CSC_D_BANK_0_DATA_BANK_DEFAULT                     (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_DEFAULT_MASK                (_MK_MASK_CONST(0xf))
+#define CSC_D_BANK_0_DATA_BANK_SW_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_PARITY_PROTECTION           (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_PLATFORM_DEPENDENT          (_MK_MASK_CONST(0x1))
+
+#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CSC_D_BANK_0_WEIGHT_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CSC_D_BANK_0_WEIGHT_BANK_SHIFT))
+#define CSC_D_BANK_0_WEIGHT_BANK_RANGE                                   (19:16)
+#define CSC_D_BANK_0_WEIGHT_BANK_WOFFSET                                   (0x0)
+#define CSC_D_BANK_0_WEIGHT_BANK_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_DEFAULT_MASK              (_MK_MASK_CONST(0xf))
+#define CSC_D_BANK_0_WEIGHT_BANK_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_PRA_CFG_0
+#define CSC_D_PRA_CFG_0                                 (_MK_ADDR_CONST(0x6060))
+#define CSC_D_PRA_CFG_0_SECURE                                             (0x0)
+#define CSC_D_PRA_CFG_0_DUAL                                               (0x0)
+#define CSC_D_PRA_CFG_0_SCR                                                  (0)
+#define CSC_D_PRA_CFG_0_WORD_COUNT                                         (0x1)
+#define CSC_D_PRA_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_RESET_MASK                         (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_READ_MASK                          (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_WRITE_MASK                         (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_RANGE                                 (1:0)
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_WOFFSET                               (0x0)
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_CYA_0
+#define CSC_D_CYA_0                                     (_MK_ADDR_CONST(0x6064))
+#define CSC_D_CYA_0_SECURE                                                 (0x0)
+#define CSC_D_CYA_0_DUAL                                                   (0x0)
+#define CSC_D_CYA_0_SCR                                                      (0)
+#define CSC_D_CYA_0_WORD_COUNT                                             (0x1)
+#define CSC_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
+#define CSC_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT))
+#define CSC_D_CYA_0_CYA_RANGE                                             (31:0)
+#define CSC_D_CYA_0_CYA_WOFFSET                                            (0x0)
+#define CSC_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
+
+
+// Register CMAC_A_S_STATUS_0
+#define CMAC_A_S_STATUS_0                               (_MK_ADDR_CONST(0x7000))
+#define CMAC_A_S_STATUS_0_SECURE                                           (0x0)
+#define CMAC_A_S_STATUS_0_DUAL                                             (0x0)
+#define CMAC_A_S_STATUS_0_SCR                                                (0)
+#define CMAC_A_S_STATUS_0_WORD_COUNT                                       (0x1)
+#define CMAC_A_S_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_RESET_MASK                   (_MK_MASK_CONST(0x30003))
+#define CMAC_A_S_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_READ_MASK                    (_MK_MASK_CONST(0x30003))
+#define CMAC_A_S_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_A_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT))
+#define CMAC_A_S_STATUS_0_STATUS_0_RANGE                                   (1:0)
+#define CMAC_A_S_STATUS_0_STATUS_0_WOFFSET                                 (0x0)
+#define CMAC_A_S_STATUS_0_STATUS_0_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_A_S_STATUS_0_STATUS_0_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_STATUS_0_STATUS_0_INIT_ENUM                              (IDLE)
+#define CMAC_A_S_STATUS_0_STATUS_0_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_A_S_STATUS_0_STATUS_0_PENDING                   (_MK_ENUM_CONST(2))
+
+#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT                   (_MK_SHIFT_CONST(16))
+#define CMAC_A_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT))
+#define CMAC_A_S_STATUS_0_STATUS_1_RANGE                                 (17:16)
+#define CMAC_A_S_STATUS_0_STATUS_1_WOFFSET                                 (0x0)
+#define CMAC_A_S_STATUS_0_STATUS_1_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_A_S_STATUS_0_STATUS_1_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_STATUS_0_STATUS_1_INIT_ENUM                              (IDLE)
+#define CMAC_A_S_STATUS_0_STATUS_1_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_A_S_STATUS_0_STATUS_1_PENDING                   (_MK_ENUM_CONST(2))
+
+
+// Register CMAC_A_S_POINTER_0
+#define CMAC_A_S_POINTER_0                              (_MK_ADDR_CONST(0x7004))
+#define CMAC_A_S_POINTER_0_SECURE                                          (0x0)
+#define CMAC_A_S_POINTER_0_DUAL                                            (0x0)
+#define CMAC_A_S_POINTER_0_SCR                                               (0)
+#define CMAC_A_S_POINTER_0_WORD_COUNT                                      (0x1)
+#define CMAC_A_S_POINTER_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_RESET_MASK                  (_MK_MASK_CONST(0x10001))
+#define CMAC_A_S_POINTER_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_READ_MASK                   (_MK_MASK_CONST(0x10001))
+#define CMAC_A_S_POINTER_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CMAC_A_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT))
+#define CMAC_A_S_POINTER_0_PRODUCER_RANGE                                  (0:0)
+#define CMAC_A_S_POINTER_0_PRODUCER_WOFFSET                                (0x0)
+#define CMAC_A_S_POINTER_0_PRODUCER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_PRODUCER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_PRODUCER_INIT_ENUM                          (GROUP_0)
+#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT                  (_MK_SHIFT_CONST(16))
+#define CMAC_A_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT))
+#define CMAC_A_S_POINTER_0_CONSUMER_RANGE                                (16:16)
+#define CMAC_A_S_POINTER_0_CONSUMER_WOFFSET                                (0x0)
+#define CMAC_A_S_POINTER_0_CONSUMER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_CONSUMER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_CONSUMER_INIT_ENUM                          (GROUP_0)
+#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_A_D_OP_ENABLE_0
+#define CMAC_A_D_OP_ENABLE_0                            (_MK_ADDR_CONST(0x7008))
+#define CMAC_A_D_OP_ENABLE_0_SECURE                                        (0x0)
+#define CMAC_A_D_OP_ENABLE_0_DUAL                                          (0x0)
+#define CMAC_A_D_OP_ENABLE_0_SCR                                             (0)
+#define CMAC_A_D_OP_ENABLE_0_WORD_COUNT                                    (0x1)
+#define CMAC_A_D_OP_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_RANGE                                   (0:0)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_WOFFSET                                 (0x0)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_INIT_ENUM                           (DISABLE)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_A_D_MISC_CFG_0
+#define CMAC_A_D_MISC_CFG_0                             (_MK_ADDR_CONST(0x700c))
+#define CMAC_A_D_MISC_CFG_0_SECURE                                         (0x0)
+#define CMAC_A_D_MISC_CFG_0_DUAL                                           (0x0)
+#define CMAC_A_D_MISC_CFG_0_SCR                                              (0)
+#define CMAC_A_D_MISC_CFG_0_WORD_COUNT                                     (0x1)
+#define CMAC_A_D_MISC_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x1000))
+#define CMAC_A_D_MISC_CFG_0_RESET_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_A_D_MISC_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_READ_MASK                   (_MK_MASK_CONST(0x3001))
+#define CMAC_A_D_MISC_CFG_0_WRITE_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_RANGE                                (0:0)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WOFFSET                              (0x0)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                         (DIRECT)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT                 (_MK_ENUM_CONST(0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD               (_MK_ENUM_CONST(1))
+
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT           (_MK_SHIFT_CONST(12))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_RANGE                         (13:12)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                         (0x0)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                     (INT16)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
+
+
+// Register CMAC_B_S_STATUS_0
+#define CMAC_B_S_STATUS_0                               (_MK_ADDR_CONST(0x8000))
+#define CMAC_B_S_STATUS_0_SECURE                                           (0x0)
+#define CMAC_B_S_STATUS_0_DUAL                                             (0x0)
+#define CMAC_B_S_STATUS_0_SCR                                                (0)
+#define CMAC_B_S_STATUS_0_WORD_COUNT                                       (0x1)
+#define CMAC_B_S_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_RESET_MASK                   (_MK_MASK_CONST(0x30003))
+#define CMAC_B_S_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_READ_MASK                    (_MK_MASK_CONST(0x30003))
+#define CMAC_B_S_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_B_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT))
+#define CMAC_B_S_STATUS_0_STATUS_0_RANGE                                   (1:0)
+#define CMAC_B_S_STATUS_0_STATUS_0_WOFFSET                                 (0x0)
+#define CMAC_B_S_STATUS_0_STATUS_0_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_B_S_STATUS_0_STATUS_0_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_STATUS_0_STATUS_0_INIT_ENUM                              (IDLE)
+#define CMAC_B_S_STATUS_0_STATUS_0_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_B_S_STATUS_0_STATUS_0_PENDING                   (_MK_ENUM_CONST(2))
+
+#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT                   (_MK_SHIFT_CONST(16))
+#define CMAC_B_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT))
+#define CMAC_B_S_STATUS_0_STATUS_1_RANGE                                 (17:16)
+#define CMAC_B_S_STATUS_0_STATUS_1_WOFFSET                                 (0x0)
+#define CMAC_B_S_STATUS_0_STATUS_1_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_B_S_STATUS_0_STATUS_1_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_STATUS_0_STATUS_1_INIT_ENUM                              (IDLE)
+#define CMAC_B_S_STATUS_0_STATUS_1_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_B_S_STATUS_0_STATUS_1_PENDING                   (_MK_ENUM_CONST(2))
+
+
+// Register CMAC_B_S_POINTER_0
+#define CMAC_B_S_POINTER_0                              (_MK_ADDR_CONST(0x8004))
+#define CMAC_B_S_POINTER_0_SECURE                                          (0x0)
+#define CMAC_B_S_POINTER_0_DUAL                                            (0x0)
+#define CMAC_B_S_POINTER_0_SCR                                               (0)
+#define CMAC_B_S_POINTER_0_WORD_COUNT                                      (0x1)
+#define CMAC_B_S_POINTER_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_RESET_MASK                  (_MK_MASK_CONST(0x10001))
+#define CMAC_B_S_POINTER_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_READ_MASK                   (_MK_MASK_CONST(0x10001))
+#define CMAC_B_S_POINTER_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CMAC_B_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT))
+#define CMAC_B_S_POINTER_0_PRODUCER_RANGE                                  (0:0)
+#define CMAC_B_S_POINTER_0_PRODUCER_WOFFSET                                (0x0)
+#define CMAC_B_S_POINTER_0_PRODUCER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_PRODUCER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_PRODUCER_INIT_ENUM                          (GROUP_0)
+#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT                  (_MK_SHIFT_CONST(16))
+#define CMAC_B_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT))
+#define CMAC_B_S_POINTER_0_CONSUMER_RANGE                                (16:16)
+#define CMAC_B_S_POINTER_0_CONSUMER_WOFFSET                                (0x0)
+#define CMAC_B_S_POINTER_0_CONSUMER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_CONSUMER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_CONSUMER_INIT_ENUM                          (GROUP_0)
+#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_B_D_OP_ENABLE_0
+#define CMAC_B_D_OP_ENABLE_0                            (_MK_ADDR_CONST(0x8008))
+#define CMAC_B_D_OP_ENABLE_0_SECURE                                        (0x0)
+#define CMAC_B_D_OP_ENABLE_0_DUAL                                          (0x0)
+#define CMAC_B_D_OP_ENABLE_0_SCR                                             (0)
+#define CMAC_B_D_OP_ENABLE_0_WORD_COUNT                                    (0x1)
+#define CMAC_B_D_OP_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_RANGE                                   (0:0)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_WOFFSET                                 (0x0)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_INIT_ENUM                           (DISABLE)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_B_D_MISC_CFG_0
+#define CMAC_B_D_MISC_CFG_0                             (_MK_ADDR_CONST(0x800c))
+#define CMAC_B_D_MISC_CFG_0_SECURE                                         (0x0)
+#define CMAC_B_D_MISC_CFG_0_DUAL                                           (0x0)
+#define CMAC_B_D_MISC_CFG_0_SCR                                              (0)
+#define CMAC_B_D_MISC_CFG_0_WORD_COUNT                                     (0x1)
+#define CMAC_B_D_MISC_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x1000))
+#define CMAC_B_D_MISC_CFG_0_RESET_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_B_D_MISC_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_READ_MASK                   (_MK_MASK_CONST(0x3001))
+#define CMAC_B_D_MISC_CFG_0_WRITE_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_RANGE                                (0:0)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WOFFSET                              (0x0)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                         (DIRECT)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT                 (_MK_ENUM_CONST(0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD               (_MK_ENUM_CONST(1))
+
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT           (_MK_SHIFT_CONST(12))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_RANGE                         (13:12)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                         (0x0)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                     (INT16)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
+
+
+// Register CACC_S_STATUS_0
+#define CACC_S_STATUS_0                                 (_MK_ADDR_CONST(0x9000))
+#define CACC_S_STATUS_0_SECURE                                             (0x0)
+#define CACC_S_STATUS_0_DUAL                                               (0x0)
+#define CACC_S_STATUS_0_SCR                                                  (0)
+#define CACC_S_STATUS_0_WORD_COUNT                                         (0x1)
+#define CACC_S_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_RESET_MASK                     (_MK_MASK_CONST(0x30003))
+#define CACC_S_STATUS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_READ_MASK                      (_MK_MASK_CONST(0x30003))
+#define CACC_S_STATUS_0_WRITE_MASK                         (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CACC_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT))
+#define CACC_S_STATUS_0_STATUS_0_RANGE                                     (1:0)
+#define CACC_S_STATUS_0_STATUS_0_WOFFSET                                   (0x0)
+#define CACC_S_STATUS_0_STATUS_0_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CACC_S_STATUS_0_STATUS_0_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CACC_S_STATUS_0_STATUS_0_INIT_ENUM                                (IDLE)
+#define CACC_S_STATUS_0_STATUS_0_IDLE                        (_MK_ENUM_CONST(0))
+#define CACC_S_STATUS_0_STATUS_0_RUNNING                     (_MK_ENUM_CONST(1))
+#define CACC_S_STATUS_0_STATUS_0_PENDING                     (_MK_ENUM_CONST(2))
+
+#define CACC_S_STATUS_0_STATUS_1_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CACC_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT))
+#define CACC_S_STATUS_0_STATUS_1_RANGE                                   (17:16)
+#define CACC_S_STATUS_0_STATUS_1_WOFFSET                                   (0x0)
+#define CACC_S_STATUS_0_STATUS_1_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CACC_S_STATUS_0_STATUS_1_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CACC_S_STATUS_0_STATUS_1_INIT_ENUM                                (IDLE)
+#define CACC_S_STATUS_0_STATUS_1_IDLE                        (_MK_ENUM_CONST(0))
+#define CACC_S_STATUS_0_STATUS_1_RUNNING                     (_MK_ENUM_CONST(1))
+#define CACC_S_STATUS_0_STATUS_1_PENDING                     (_MK_ENUM_CONST(2))
+
+
+// Register CACC_S_POINTER_0
+#define CACC_S_POINTER_0                                (_MK_ADDR_CONST(0x9004))
+#define CACC_S_POINTER_0_SECURE                                            (0x0)
+#define CACC_S_POINTER_0_DUAL                                              (0x0)
+#define CACC_S_POINTER_0_SCR                                                 (0)
+#define CACC_S_POINTER_0_WORD_COUNT                                        (0x1)
+#define CACC_S_POINTER_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_RESET_MASK                    (_MK_MASK_CONST(0x10001))
+#define CACC_S_POINTER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_READ_MASK                     (_MK_MASK_CONST(0x10001))
+#define CACC_S_POINTER_0_WRITE_MASK                        (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_PRODUCER_SHIFT                     (_MK_SHIFT_CONST(0))
+#define CACC_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT))
+#define CACC_S_POINTER_0_PRODUCER_RANGE                                    (0:0)
+#define CACC_S_POINTER_0_PRODUCER_WOFFSET                                  (0x0)
+#define CACC_S_POINTER_0_PRODUCER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_PRODUCER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_PRODUCER_INIT_ENUM                            (GROUP_0)
+#define CACC_S_POINTER_0_PRODUCER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CACC_S_POINTER_0_PRODUCER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+#define CACC_S_POINTER_0_CONSUMER_SHIFT                    (_MK_SHIFT_CONST(16))
+#define CACC_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT))
+#define CACC_S_POINTER_0_CONSUMER_RANGE                                  (16:16)
+#define CACC_S_POINTER_0_CONSUMER_WOFFSET                                  (0x0)
+#define CACC_S_POINTER_0_CONSUMER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_CONSUMER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_CONSUMER_INIT_ENUM                            (GROUP_0)
+#define CACC_S_POINTER_0_CONSUMER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CACC_S_POINTER_0_CONSUMER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+
+// Register CACC_D_OP_ENABLE_0
+#define CACC_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x9008))
+#define CACC_D_OP_ENABLE_0_SECURE                                          (0x0)
+#define CACC_D_OP_ENABLE_0_DUAL                                            (0x0)
+#define CACC_D_OP_ENABLE_0_SCR                                               (0)
+#define CACC_D_OP_ENABLE_0_WORD_COUNT                                      (0x1)
+#define CACC_D_OP_ENABLE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CACC_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CACC_D_OP_ENABLE_0_OP_EN_RANGE                                     (0:0)
+#define CACC_D_OP_ENABLE_0_OP_EN_WOFFSET                                   (0x0)
+#define CACC_D_OP_ENABLE_0_OP_EN_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_OP_EN_INIT_ENUM                             (DISABLE)
+#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE                     (_MK_ENUM_CONST(0))
+#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE                      (_MK_ENUM_CONST(1))
+
+
+// Register CACC_D_MISC_CFG_0
+#define CACC_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x900c))
+#define CACC_D_MISC_CFG_0_SECURE                                           (0x0)
+#define CACC_D_MISC_CFG_0_DUAL                                             (0x0)
+#define CACC_D_MISC_CFG_0_SCR                                                (0)
+#define CACC_D_MISC_CFG_0_WORD_COUNT                                       (0x1)
+#define CACC_D_MISC_CFG_0_RESET_VAL                     (_MK_MASK_CONST(0x1000))
+#define CACC_D_MISC_CFG_0_RESET_MASK                    (_MK_MASK_CONST(0x3001))
+#define CACC_D_MISC_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_READ_MASK                     (_MK_MASK_CONST(0x3001))
+#define CACC_D_MISC_CFG_0_WRITE_MASK                    (_MK_MASK_CONST(0x3001))
+#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CACC_D_MISC_CFG_0_CONV_MODE_RANGE                                  (0:0)
+#define CACC_D_MISC_CFG_0_CONV_MODE_WOFFSET                                (0x0)
+#define CACC_D_MISC_CFG_0_CONV_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                           (DIRECT)
+#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT                   (_MK_ENUM_CONST(0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                 (_MK_ENUM_CONST(1))
+
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT             (_MK_SHIFT_CONST(12))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_RANGE                           (13:12)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                           (0x0)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT           (_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK      (_MK_MASK_CONST(0x3))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                       (INT16)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8                (_MK_ENUM_CONST(0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16               (_MK_ENUM_CONST(1))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16                (_MK_ENUM_CONST(2))
+
+
+// Register CACC_D_DATAOUT_SIZE_0_0
+#define CACC_D_DATAOUT_SIZE_0_0                         (_MK_ADDR_CONST(0x9010))
+#define CACC_D_DATAOUT_SIZE_0_0_SECURE                                     (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_DUAL                                       (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_SCR                                          (0)
+#define CACC_D_DATAOUT_SIZE_0_0_WORD_COUNT                                 (0x1)
+#define CACC_D_DATAOUT_SIZE_0_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_RESET_MASK          (_MK_MASK_CONST(0x1fff1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_READ_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT         (_MK_SHIFT_CONST(0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_RANGE                       (12:0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_WOFFSET                      (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT       (_MK_SHIFT_CONST(16))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_RANGE                     (28:16)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_WOFFSET                     (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_DATAOUT_SIZE_1_0
+#define CACC_D_DATAOUT_SIZE_1_0                         (_MK_ADDR_CONST(0x9014))
+#define CACC_D_DATAOUT_SIZE_1_0_SECURE                                     (0x0)
+#define CACC_D_DATAOUT_SIZE_1_0_DUAL                                       (0x0)
+#define CACC_D_DATAOUT_SIZE_1_0_SCR                                          (0)
+#define CACC_D_DATAOUT_SIZE_1_0_WORD_COUNT                                 (0x1)
+#define CACC_D_DATAOUT_SIZE_1_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_RESET_MASK              (_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_READ_MASK               (_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_WRITE_MASK              (_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT       (_MK_SHIFT_CONST(0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                     (12:0)
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                    (0x0)
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_DATAOUT_ADDR_0
+#define CACC_D_DATAOUT_ADDR_0                           (_MK_ADDR_CONST(0x9018))
+#define CACC_D_DATAOUT_ADDR_0_SECURE                                       (0x0)
+#define CACC_D_DATAOUT_ADDR_0_DUAL                                         (0x0)
+#define CACC_D_DATAOUT_ADDR_0_SCR                                            (0)
+#define CACC_D_DATAOUT_ADDR_0_WORD_COUNT                                   (0x1)
+#define CACC_D_DATAOUT_ADDR_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CACC_D_DATAOUT_ADDR_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CACC_D_DATAOUT_ADDR_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT            (_MK_SHIFT_CONST(5))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_RANGE                          (31:5)
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_WOFFSET                         (0x0)
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_BATCH_NUMBER_0
+#define CACC_D_BATCH_NUMBER_0                           (_MK_ADDR_CONST(0x901c))
+#define CACC_D_BATCH_NUMBER_0_SECURE                                       (0x0)
+#define CACC_D_BATCH_NUMBER_0_DUAL                                         (0x0)
+#define CACC_D_BATCH_NUMBER_0_SCR                                            (0)
+#define CACC_D_BATCH_NUMBER_0_WORD_COUNT                                   (0x1)
+#define CACC_D_BATCH_NUMBER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD \
+	(_MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_RANGE                                (4:0)
+#define CACC_D_BATCH_NUMBER_0_BATCHES_WOFFSET                              (0x0)
+#define CACC_D_BATCH_NUMBER_0_BATCHES_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_LINE_STRIDE_0
+#define CACC_D_LINE_STRIDE_0                            (_MK_ADDR_CONST(0x9020))
+#define CACC_D_LINE_STRIDE_0_SECURE                                        (0x0)
+#define CACC_D_LINE_STRIDE_0_DUAL                                          (0x0)
+#define CACC_D_LINE_STRIDE_0_SCR                                             (0)
+#define CACC_D_LINE_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CACC_D_LINE_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_RESET_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_LINE_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_READ_MASK                (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_LINE_STRIDE_0_WRITE_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_RANGE                            (23:5)
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_WOFFSET                           (0x0)
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_SURF_STRIDE_0
+#define CACC_D_SURF_STRIDE_0                            (_MK_ADDR_CONST(0x9024))
+#define CACC_D_SURF_STRIDE_0_SECURE                                        (0x0)
+#define CACC_D_SURF_STRIDE_0_DUAL                                          (0x0)
+#define CACC_D_SURF_STRIDE_0_SCR                                             (0)
+#define CACC_D_SURF_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CACC_D_SURF_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_RESET_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_SURF_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_READ_MASK                (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_SURF_STRIDE_0_WRITE_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_RANGE                            (23:5)
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_WOFFSET                           (0x0)
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_DATAOUT_MAP_0
+#define CACC_D_DATAOUT_MAP_0                            (_MK_ADDR_CONST(0x9028))
+#define CACC_D_DATAOUT_MAP_0_SECURE                                        (0x0)
+#define CACC_D_DATAOUT_MAP_0_DUAL                                          (0x0)
+#define CACC_D_DATAOUT_MAP_0_SCR                                             (0)
+#define CACC_D_DATAOUT_MAP_0_WORD_COUNT                                    (0x1)
+#define CACC_D_DATAOUT_MAP_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define CACC_D_DATAOUT_MAP_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define CACC_D_DATAOUT_MAP_0_WRITE_MASK                (_MK_MASK_CONST(0x10001))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT              (_MK_SHIFT_CONST(0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_RANGE                             (0:0)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_WOFFSET                           (0x0)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_INIT_ENUM                       (FALSE)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE               (_MK_ENUM_CONST(0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE                (_MK_ENUM_CONST(1))
+
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT             (_MK_SHIFT_CONST(16))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_RANGE                           (16:16)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_WOFFSET                           (0x0)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_INIT_ENUM                       (FALSE)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE               (_MK_ENUM_CONST(0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE                (_MK_ENUM_CONST(1))
+
+
+// Register CACC_D_CLIP_CFG_0
+#define CACC_D_CLIP_CFG_0                               (_MK_ADDR_CONST(0x902c))
+#define CACC_D_CLIP_CFG_0_SECURE                                           (0x0)
+#define CACC_D_CLIP_CFG_0_DUAL                                             (0x0)
+#define CACC_D_CLIP_CFG_0_SCR                                                (0)
+#define CACC_D_CLIP_CFG_0_WORD_COUNT                                       (0x1)
+#define CACC_D_CLIP_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT               (_MK_SHIFT_CONST(0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_RANGE                              (4:0)
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_WOFFSET                            (0x0)
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_DEFAULT_MASK      (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_OUT_SATURATION_0
+#define CACC_D_OUT_SATURATION_0                         (_MK_ADDR_CONST(0x9030))
+#define CACC_D_OUT_SATURATION_0_SECURE                                     (0x0)
+#define CACC_D_OUT_SATURATION_0_DUAL                                       (0x0)
+#define CACC_D_OUT_SATURATION_0_SCR                                          (0)
+#define CACC_D_OUT_SATURATION_0_WORD_COUNT                                 (0x1)
+#define CACC_D_OUT_SATURATION_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_OUT_SATURATION_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_OUT_SATURATION_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT             (_MK_SHIFT_CONST(0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_RANGE                           (31:0)
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_WOFFSET                          (0x0)
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_CYA_0
+#define CACC_D_CYA_0                                    (_MK_ADDR_CONST(0x9034))
+#define CACC_D_CYA_0_SECURE                                                (0x0)
+#define CACC_D_CYA_0_DUAL                                                  (0x0)
+#define CACC_D_CYA_0_SCR                                                     (0)
+#define CACC_D_CYA_0_WORD_COUNT                                            (0x1)
+#define CACC_D_CYA_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_RESET_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_READ_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_WRITE_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_CYA_SHIFT                              (_MK_SHIFT_CONST(0))
+#define CACC_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT))
+#define CACC_D_CYA_0_CYA_RANGE                                            (31:0)
+#define CACC_D_CYA_0_CYA_WOFFSET                                           (0x0)
+#define CACC_D_CYA_0_CYA_DEFAULT                           (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_CYA_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_S_STATUS_0
+#define SDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xa000))
+#define SDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
+#define SDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
+#define SDP_RDMA_S_STATUS_0_SCR                                              (0)
+#define SDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
+#define SDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
+#define SDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
+#define SDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
+
+
+// Register SDP_RDMA_S_POINTER_0
+#define SDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xa004))
+#define SDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
+#define SDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
+#define SDP_RDMA_S_POINTER_0_SCR                                             (0)
+#define SDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
+#define SDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define SDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define SDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_OP_ENABLE_0
+#define SDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xa008))
+#define SDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
+#define SDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0                    (_MK_ADDR_CONST(0xa00c))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SECURE                                (0x0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SCR                                     (0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                          (12:0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                         (0x0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0                   (_MK_ADDR_CONST(0xa010))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SECURE                               (0x0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SCR                                    (0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                        (12:0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                       (0x0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0                  (_MK_ADDR_CONST(0xa014))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SECURE                              (0x0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_DUAL                                (0x0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SCR                                   (0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_MASK       (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_READ_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                      (12:0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                     (0x0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xa018))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xa01c))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_LINE_STRIDE_0
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xa020))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xa024))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BRDMA_CFG_0
+#define SDP_RDMA_D_BRDMA_CFG_0                          (_MK_ADDR_CONST(0xa028))
+#define SDP_RDMA_D_BRDMA_CFG_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_SCR                                           (0)
+#define SDP_RDMA_D_BRDMA_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_BRDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_BRDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_BRDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_RANGE                         (0:0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_WOFFSET                       (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_RANGE                        (2:1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_RANGE                       (3:3)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_RANGE                       (4:4)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT \
+	(_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_RANGE                        (5:5)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa02c))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SECURE                               (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SCR                                    (0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_RANGE              (31:5)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_WOFFSET             (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa030))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SCR                                   (0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_RANGE            (31:0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_WOFFSET           (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_LINE_STRIDE_0
+#define SDP_RDMA_D_BS_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa034))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SECURE                                 (0x0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_DUAL                                   (0x0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SCR                                      (0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_WORD_COUNT                             (0x1)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_RANGE                  (31:5)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_WOFFSET                 (0x0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa038))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SCR                                   (0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_RANGE            (31:5)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_WOFFSET           (0x0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_BATCH_STRIDE_0
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa03c))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_NRDMA_CFG_0
+#define SDP_RDMA_D_NRDMA_CFG_0                          (_MK_ADDR_CONST(0xa040))
+#define SDP_RDMA_D_NRDMA_CFG_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_SCR                                           (0)
+#define SDP_RDMA_D_NRDMA_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_NRDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_NRDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_NRDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_RANGE                         (0:0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_WOFFSET                       (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_RANGE                        (2:1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_RANGE                       (3:3)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_RANGE                       (4:4)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT \
+	(_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_RANGE                        (5:5)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa044))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SECURE                               (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SCR                                    (0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_RANGE              (31:5)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_WOFFSET             (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa048))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SCR                                   (0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_RANGE            (31:0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_WOFFSET           (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_LINE_STRIDE_0
+#define SDP_RDMA_D_BN_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa04c))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SECURE                                 (0x0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_DUAL                                   (0x0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SCR                                      (0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_WORD_COUNT                             (0x1)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_RANGE                  (31:5)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_WOFFSET                 (0x0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa050))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SCR                                   (0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_RANGE            (31:5)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_WOFFSET           (0x0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_BATCH_STRIDE_0
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa054))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_ERDMA_CFG_0
+#define SDP_RDMA_D_ERDMA_CFG_0                          (_MK_ADDR_CONST(0xa058))
+#define SDP_RDMA_D_ERDMA_CFG_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_SCR                                           (0)
+#define SDP_RDMA_D_ERDMA_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_ERDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_ERDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_ERDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_RANGE                         (0:0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_WOFFSET                       (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_RANGE                        (2:1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_RANGE                       (3:3)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_RANGE                       (4:4)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT \
+	(_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_RANGE                        (5:5)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa05c))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SECURE                               (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SCR                                    (0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_RANGE              (31:5)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_WOFFSET             (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa060))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SECURE                              (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_DUAL                                (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SCR                                   (0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_RANGE            (31:0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_WOFFSET           (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_LINE_STRIDE_0
+#define SDP_RDMA_D_EW_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa064))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SECURE                                 (0x0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_DUAL                                   (0x0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SCR                                      (0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_WORD_COUNT                             (0x1)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_RANGE                  (31:5)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_WOFFSET                 (0x0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa068))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SECURE                              (0x0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_DUAL                                (0x0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SCR                                   (0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_RANGE            (31:5)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_WOFFSET           (0x0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_BATCH_STRIDE_0
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa06c))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_FEATURE_MODE_CFG_0
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0                   (_MK_ADDR_CONST(0xa070))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SECURE                               (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SCR                                    (0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_RESET_VAL           (_MK_MASK_CONST(0x14))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT     (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_RANGE                    (0:0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_WOFFSET                  (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF        (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON         (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT        (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_RANGE                       (1:1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_WOFFSET                     (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF           (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON            (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT    (_MK_SHIFT_CONST(2))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_RANGE                   (3:2)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_WOFFSET                 (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16     (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16      (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT \
+	(_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_RANGE                 (5:4)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_WOFFSET               (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16 \
+	(_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16    (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT \
+	(_MK_SHIFT_CONST(6))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_RANGE                  (7:6)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_WOFFSET                (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8     (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16    (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16     (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT    (_MK_SHIFT_CONST(8))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_RANGE                  (12:8)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_WOFFSET                 (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_DMA_CFG_0
+#define SDP_RDMA_D_SRC_DMA_CFG_0                        (_MK_ADDR_CONST(0xa074))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SECURE                                    (0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_DUAL                                      (0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SCR                                         (0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_WORD_COUNT                                (0x1)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0               (_MK_ADDR_CONST(0xa078))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SECURE                           (0x0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_DUAL                             (0x0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SCR                                (0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_WORD_COUNT                       (0x1)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_WRITE_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_RANGE      (31:0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_WOFFSET     (0x0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0               (_MK_ADDR_CONST(0xa07c))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SECURE                           (0x0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_DUAL                             (0x0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SCR                                (0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_WORD_COUNT                       (0x1)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_WRITE_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_RANGE      (31:0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_WOFFSET     (0x0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_ENABLE_0
+#define SDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xa080))
+#define SDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
+#define SDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
+#define SDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_RANGE                         (0:0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_WOFFSET                       (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_INIT_ENUM                      (NO)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT \
+	(_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_RANGE               (1:1)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_INIT_ENUM            (NO)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES \
+	(_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa084))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa088))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa08c))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa090))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_STATUS_0
+#define SDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xb000))
+#define SDP_S_STATUS_0_SECURE                                              (0x0)
+#define SDP_S_STATUS_0_DUAL                                                (0x0)
+#define SDP_S_STATUS_0_SCR                                                   (0)
+#define SDP_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define SDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define SDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define SDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define SDP_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT))
+#define SDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define SDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define SDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define SDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define SDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define SDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define SDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define SDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define SDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define SDP_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT))
+#define SDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define SDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define SDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define SDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define SDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define SDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define SDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define SDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register SDP_S_POINTER_0
+#define SDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xb004))
+#define SDP_S_POINTER_0_SECURE                                             (0x0)
+#define SDP_S_POINTER_0_DUAL                                               (0x0)
+#define SDP_S_POINTER_0_SCR                                                  (0)
+#define SDP_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define SDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define SDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define SDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define SDP_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT))
+#define SDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define SDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define SDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define SDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define SDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define SDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define SDP_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT))
+#define SDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define SDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define SDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define SDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define SDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register SDP_S_LUT_ACCESS_CFG_0
+#define SDP_S_LUT_ACCESS_CFG_0                          (_MK_ADDR_CONST(0xb008))
+#define SDP_S_LUT_ACCESS_CFG_0_SECURE                                      (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_DUAL                                        (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_SCR                                           (0)
+#define SDP_S_LUT_ACCESS_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_S_LUT_ACCESS_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_RESET_MASK              (_MK_MASK_CONST(0x303ff))
+#define SDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_READ_MASK               (_MK_MASK_CONST(0x303ff))
+#define SDP_S_LUT_ACCESS_CFG_0_WRITE_MASK              (_MK_MASK_CONST(0x303ff))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD \
+	(_MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_RANGE                              (9:0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_WOFFSET                            (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT_MASK     (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT          (_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_RANGE                        (16:16)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_WOFFSET                        (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_INIT_ENUM                       (LE)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE               (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO               (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT       (_MK_SHIFT_CONST(17))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_RANGE                     (17:17)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WOFFSET                     (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_INIT_ENUM                  (READ)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ          (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE         (_MK_ENUM_CONST(1))
+
+
+// Register SDP_S_LUT_ACCESS_DATA_0
+#define SDP_S_LUT_ACCESS_DATA_0                         (_MK_ADDR_CONST(0xb00c))
+#define SDP_S_LUT_ACCESS_DATA_0_SECURE                                     (0x0)
+#define SDP_S_LUT_ACCESS_DATA_0_DUAL                                       (0x0)
+#define SDP_S_LUT_ACCESS_DATA_0_SCR                                          (0)
+#define SDP_S_LUT_ACCESS_DATA_0_WORD_COUNT                                 (0x1)
+#define SDP_S_LUT_ACCESS_DATA_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_RESET_MASK              (_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_READ_MASK               (_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_WRITE_MASK              (_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_RANGE                            (15:0)
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_WOFFSET                           (0x0)
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_CFG_0
+#define SDP_S_LUT_CFG_0                                 (_MK_ADDR_CONST(0xb010))
+#define SDP_S_LUT_CFG_0_SECURE                                             (0x0)
+#define SDP_S_LUT_CFG_0_DUAL                                               (0x0)
+#define SDP_S_LUT_CFG_0_SCR                                                  (0)
+#define SDP_S_LUT_CFG_0_WORD_COUNT                                         (0x1)
+#define SDP_S_LUT_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_RESET_MASK                        (_MK_MASK_CONST(0x71))
+#define SDP_S_LUT_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_READ_MASK                         (_MK_MASK_CONST(0x71))
+#define SDP_S_LUT_CFG_0_WRITE_MASK                        (_MK_MASK_CONST(0x71))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_RANGE                              (0:0)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_WOFFSET                            (0x0)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_INIT_ENUM                     (EXPONENT)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT             (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR               (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(4))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_RANGE                           (4:4)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_WOFFSET                         (0x0)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(5))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_RANGE                           (5:5)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_WOFFSET                         (0x0)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT           (_MK_SHIFT_CONST(6))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_RANGE                          (6:6)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_WOFFSET                        (0x0)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE               (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO               (_MK_ENUM_CONST(1))
+
+
+// Register SDP_S_LUT_INFO_0
+#define SDP_S_LUT_INFO_0                                (_MK_ADDR_CONST(0xb014))
+#define SDP_S_LUT_INFO_0_SECURE                                            (0x0)
+#define SDP_S_LUT_INFO_0_DUAL                                              (0x0)
+#define SDP_S_LUT_INFO_0_SCR                                                 (0)
+#define SDP_S_LUT_INFO_0_WORD_COUNT                                        (0x1)
+#define SDP_S_LUT_INFO_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_RESET_MASK                   (_MK_MASK_CONST(0xffffff))
+#define SDP_S_LUT_INFO_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_READ_MASK                    (_MK_MASK_CONST(0xffffff))
+#define SDP_S_LUT_INFO_0_WRITE_MASK                   (_MK_MASK_CONST(0xffffff))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_RANGE                         (7:0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_WOFFSET                       (0x0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT          (_MK_SHIFT_CONST(8))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD \
+	(_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_RANGE                        (15:8)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_WOFFSET                       (0x0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT         (_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD \
+	(_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_RANGE                       (23:16)
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_WOFFSET                       (0x0)
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_START_0
+#define SDP_S_LUT_LE_START_0                            (_MK_ADDR_CONST(0xb018))
+#define SDP_S_LUT_LE_START_0_SECURE                                        (0x0)
+#define SDP_S_LUT_LE_START_0_DUAL                                          (0x0)
+#define SDP_S_LUT_LE_START_0_SCR                                             (0)
+#define SDP_S_LUT_LE_START_0_WORD_COUNT                                    (0x1)
+#define SDP_S_LUT_LE_START_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_RESET_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_READ_MASK              (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT             (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_RANGE                           (31:0)
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_WOFFSET                          (0x0)
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_END_0
+#define SDP_S_LUT_LE_END_0                              (_MK_ADDR_CONST(0xb01c))
+#define SDP_S_LUT_LE_END_0_SECURE                                          (0x0)
+#define SDP_S_LUT_LE_END_0_DUAL                                            (0x0)
+#define SDP_S_LUT_LE_END_0_SCR                                               (0)
+#define SDP_S_LUT_LE_END_0_WORD_COUNT                                      (0x1)
+#define SDP_S_LUT_LE_END_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_RANGE                               (31:0)
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_WOFFSET                              (0x0)
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_START_0
+#define SDP_S_LUT_LO_START_0                            (_MK_ADDR_CONST(0xb020))
+#define SDP_S_LUT_LO_START_0_SECURE                                        (0x0)
+#define SDP_S_LUT_LO_START_0_DUAL                                          (0x0)
+#define SDP_S_LUT_LO_START_0_SCR                                             (0)
+#define SDP_S_LUT_LO_START_0_WORD_COUNT                                    (0x1)
+#define SDP_S_LUT_LO_START_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_RESET_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_READ_MASK              (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT             (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_RANGE                           (31:0)
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_WOFFSET                          (0x0)
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_END_0
+#define SDP_S_LUT_LO_END_0                              (_MK_ADDR_CONST(0xb024))
+#define SDP_S_LUT_LO_END_0_SECURE                                          (0x0)
+#define SDP_S_LUT_LO_END_0_DUAL                                            (0x0)
+#define SDP_S_LUT_LO_END_0_SCR                                               (0)
+#define SDP_S_LUT_LO_END_0_WORD_COUNT                                      (0x1)
+#define SDP_S_LUT_LO_END_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_RANGE                               (31:0)
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_WOFFSET                              (0x0)
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_SLOPE_SCALE_0
+#define SDP_S_LUT_LE_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xb028))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SCR                                       (0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_RANGE         (15:0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_RANGE        (31:16)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_SLOPE_SHIFT_0
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xb02c))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SCR                                       (0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_SLOPE_SCALE_0
+#define SDP_S_LUT_LO_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xb030))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SCR                                       (0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_RANGE         (15:0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_RANGE        (31:16)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_SLOPE_SHIFT_0
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xb034))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SCR                                       (0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_OP_ENABLE_0
+#define SDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xb038))
+#define SDP_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define SDP_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define SDP_D_OP_ENABLE_0_SCR                                                (0)
+#define SDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define SDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define SDP_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define SDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define SDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define SDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DATA_CUBE_WIDTH_0
+#define SDP_D_DATA_CUBE_WIDTH_0                         (_MK_ADDR_CONST(0xb03c))
+#define SDP_D_DATA_CUBE_WIDTH_0_SECURE                                     (0x0)
+#define SDP_D_DATA_CUBE_WIDTH_0_DUAL                                       (0x0)
+#define SDP_D_DATA_CUBE_WIDTH_0_SCR                                          (0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WORD_COUNT                                 (0x1)
+#define SDP_D_DATA_CUBE_WIDTH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_RESET_MASK              (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_READ_MASK               (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_WRITE_MASK              (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                               (12:0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                              (0x0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK      (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DATA_CUBE_HEIGHT_0
+#define SDP_D_DATA_CUBE_HEIGHT_0                        (_MK_ADDR_CONST(0xb040))
+#define SDP_D_DATA_CUBE_HEIGHT_0_SECURE                                    (0x0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_DUAL                                      (0x0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_SCR                                         (0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                                (0x1)
+#define SDP_D_DATA_CUBE_HEIGHT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_RESET_MASK             (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_READ_MASK              (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_WRITE_MASK             (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                             (12:0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                            (0x0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK    (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DATA_CUBE_CHANNEL_0
+#define SDP_D_DATA_CUBE_CHANNEL_0                       (_MK_ADDR_CONST(0xb044))
+#define SDP_D_DATA_CUBE_CHANNEL_0_SECURE                                   (0x0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_DUAL                                     (0x0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_SCR                                        (0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                               (0x1)
+#define SDP_D_DATA_CUBE_CHANNEL_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_RESET_MASK            (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_READ_MASK             (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT             (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                           (12:0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                          (0x0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_BASE_ADDR_LOW_0
+#define SDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xb048))
+#define SDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define SDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_BASE_ADDR_HIGH_0
+#define SDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xb04c))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_LINE_STRIDE_0
+#define SDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xb050))
+#define SDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
+#define SDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
+#define SDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
+#define SDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define SDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_SURFACE_STRIDE_0
+#define SDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xb054))
+#define SDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define SDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define SDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
+#define SDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define SDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_CFG_0
+#define SDP_D_DP_BS_CFG_0                               (_MK_ADDR_CONST(0xb058))
+#define SDP_D_DP_BS_CFG_0_SECURE                                           (0x0)
+#define SDP_D_DP_BS_CFG_0_DUAL                                             (0x0)
+#define SDP_D_DP_BS_CFG_0_SCR                                                (0)
+#define SDP_D_DP_BS_CFG_0_WORD_COUNT                                       (0x1)
+#define SDP_D_DP_BS_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BS_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BS_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_RANGE                                  (0:0)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_WOFFSET                                (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO                       (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES                      (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_RANGE                              (1:1)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_RANGE                                (3:2)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_WOFFSET                              (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
+
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_RANGE                              (4:4)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_RANGE                               (5:5)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_WOFFSET                             (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT              (_MK_SHIFT_CONST(6))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_RANGE                             (6:6)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_WOFFSET                           (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO                  (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES                 (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_BS_ALU_CFG_0
+#define SDP_D_DP_BS_ALU_CFG_0                           (_MK_ADDR_CONST(0xb05c))
+#define SDP_D_DP_BS_ALU_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BS_ALU_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BS_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BS_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BS_ALU_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_RANGE                    (13:8)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_ALU_SRC_VALUE_0
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb060))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_MUL_CFG_0
+#define SDP_D_DP_BS_MUL_CFG_0                           (_MK_ADDR_CONST(0xb064))
+#define SDP_D_DP_BS_MUL_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BS_MUL_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BS_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_RESET_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BS_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_READ_MASK                 (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BS_MUL_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_RANGE                    (15:8)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_MUL_SRC_VALUE_0
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb068))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_CFG_0
+#define SDP_D_DP_BN_CFG_0                               (_MK_ADDR_CONST(0xb06c))
+#define SDP_D_DP_BN_CFG_0_SECURE                                           (0x0)
+#define SDP_D_DP_BN_CFG_0_DUAL                                             (0x0)
+#define SDP_D_DP_BN_CFG_0_SCR                                                (0)
+#define SDP_D_DP_BN_CFG_0_WORD_COUNT                                       (0x1)
+#define SDP_D_DP_BN_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BN_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BN_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_RANGE                                  (0:0)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_WOFFSET                                (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO                       (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES                      (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_RANGE                              (1:1)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_RANGE                                (3:2)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_WOFFSET                              (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
+
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_RANGE                              (4:4)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_RANGE                               (5:5)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_WOFFSET                             (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT              (_MK_SHIFT_CONST(6))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_RANGE                             (6:6)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_WOFFSET                           (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO                  (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES                 (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_BN_ALU_CFG_0
+#define SDP_D_DP_BN_ALU_CFG_0                           (_MK_ADDR_CONST(0xb070))
+#define SDP_D_DP_BN_ALU_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BN_ALU_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BN_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BN_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BN_ALU_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_RANGE                    (13:8)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_ALU_SRC_VALUE_0
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb074))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_MUL_CFG_0
+#define SDP_D_DP_BN_MUL_CFG_0                           (_MK_ADDR_CONST(0xb078))
+#define SDP_D_DP_BN_MUL_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BN_MUL_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BN_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_RESET_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BN_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_READ_MASK                 (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BN_MUL_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_RANGE                    (15:8)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_MUL_SRC_VALUE_0
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb07c))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_CFG_0
+#define SDP_D_DP_EW_CFG_0                               (_MK_ADDR_CONST(0xb080))
+#define SDP_D_DP_EW_CFG_0_SECURE                                           (0x0)
+#define SDP_D_DP_EW_CFG_0_DUAL                                             (0x0)
+#define SDP_D_DP_EW_CFG_0_SCR                                                (0)
+#define SDP_D_DP_EW_CFG_0_WORD_COUNT                                       (0x1)
+#define SDP_D_DP_EW_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_EW_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_EW_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_RANGE                                  (0:0)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_WOFFSET                                (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO                       (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES                      (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_RANGE                              (1:1)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_RANGE                                (3:2)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_WOFFSET                              (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL                    (_MK_ENUM_CONST(3))
+
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_RANGE                              (4:4)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_RANGE                               (5:5)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_WOFFSET                             (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT               (_MK_SHIFT_CONST(6))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_RANGE                              (6:6)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_EW_ALU_CFG_0
+#define SDP_D_DP_EW_ALU_CFG_0                           (_MK_ADDR_CONST(0xb084))
+#define SDP_D_DP_EW_ALU_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_SCR                                            (0)
+#define SDP_D_DP_EW_ALU_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_EW_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_RESET_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_READ_MASK                    (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_ALU_CFG_0_WRITE_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_RANGE                             (0:0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT       (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_RANGE                      (1:1)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_WOFFSET                    (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO           (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES          (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_EW_ALU_SRC_VALUE_0
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb088))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_RANGE                  (31:0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0              (_MK_ADDR_CONST(0xb08c))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SECURE                          (0x0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_DUAL                            (0x0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SCR                               (0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_WORD_COUNT                      (0x1)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_RANGE        (31:0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_WOFFSET       (0x0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0               (_MK_ADDR_CONST(0xb090))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SECURE                           (0x0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_DUAL                             (0x0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SCR                                (0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_WORD_COUNT                       (0x1)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_RESET_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_READ_MASK     (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_WRITE_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_RANGE          (15:0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_WOFFSET         (0x0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0            (_MK_ADDR_CONST(0xb094))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SECURE                        (0x0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_DUAL                          (0x0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SCR                             (0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_WORD_COUNT                    (0x1)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_RESET_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_READ_MASK    (_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_RANGE     (5:0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_WOFFSET \
+	(0x0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CFG_0
+#define SDP_D_DP_EW_MUL_CFG_0                           (_MK_ADDR_CONST(0xb098))
+#define SDP_D_DP_EW_MUL_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_SCR                                            (0)
+#define SDP_D_DP_EW_MUL_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_EW_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_RESET_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_READ_MASK                    (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_MUL_CFG_0_WRITE_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_RANGE                             (0:0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT       (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_RANGE                      (1:1)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_WOFFSET                    (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO           (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES          (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_EW_MUL_SRC_VALUE_0
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb09c))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_RANGE                  (31:0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0              (_MK_ADDR_CONST(0xb0a0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SECURE                          (0x0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_DUAL                            (0x0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SCR                               (0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_WORD_COUNT                      (0x1)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_RANGE        (31:0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_WOFFSET       (0x0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0               (_MK_ADDR_CONST(0xb0a4))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SECURE                           (0x0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_DUAL                             (0x0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SCR                                (0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_WORD_COUNT                       (0x1)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_RESET_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_READ_MASK     (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_WRITE_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_RANGE          (15:0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_WOFFSET         (0x0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0            (_MK_ADDR_CONST(0xb0a8))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SECURE                        (0x0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_DUAL                          (0x0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SCR                             (0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_WORD_COUNT                    (0x1)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_RESET_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_READ_MASK    (_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_RANGE     (5:0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_WOFFSET \
+	(0x0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0                    (_MK_ADDR_CONST(0xb0ac))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SECURE                                (0x0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_DUAL                                  (0x0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SCR                                     (0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_WORD_COUNT                            (0x1)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_READ_MASK           (_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT      (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_RANGE                     (9:0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_WOFFSET                   (0x0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_FEATURE_MODE_CFG_0
+#define SDP_D_FEATURE_MODE_CFG_0                        (_MK_ADDR_CONST(0xb0b0))
+#define SDP_D_FEATURE_MODE_CFG_0_SECURE                                    (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_DUAL                                      (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_SCR                                         (0)
+#define SDP_D_FEATURE_MODE_CFG_0_WORD_COUNT                                (0x1)
+#define SDP_D_FEATURE_MODE_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_RESET_MASK             (_MK_MASK_CONST(0x1f0f))
+#define SDP_D_FEATURE_MODE_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_READ_MASK              (_MK_MASK_CONST(0x1f0f))
+#define SDP_D_FEATURE_MODE_CFG_0_WRITE_MASK             (_MK_MASK_CONST(0x1f0f))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_RANGE                         (0:0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_WOFFSET                       (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF             (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON              (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT           (_MK_SHIFT_CONST(1))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_RANGE                          (1:1)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_WOFFSET                        (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM              (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP              (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT             (_MK_SHIFT_CONST(2))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_RANGE                            (2:2)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_WOFFSET                          (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF                (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT          (_MK_SHIFT_CONST(3))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_RANGE                         (3:3)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_WOFFSET                       (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_INIT_ENUM                 (DISABLE)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE         (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE          (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT         (_MK_SHIFT_CONST(8))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_RANGE                       (12:8)
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_WOFFSET                      (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_DMA_CFG_0
+#define SDP_D_DST_DMA_CFG_0                             (_MK_ADDR_CONST(0xb0b4))
+#define SDP_D_DST_DMA_CFG_0_SECURE                                         (0x0)
+#define SDP_D_DST_DMA_CFG_0_DUAL                                           (0x0)
+#define SDP_D_DST_DMA_CFG_0_SCR                                              (0)
+#define SDP_D_DST_DMA_CFG_0_WORD_COUNT                                     (0x1)
+#define SDP_D_DST_DMA_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DST_BATCH_STRIDE_0
+#define SDP_D_DST_BATCH_STRIDE_0                        (_MK_ADDR_CONST(0xb0b8))
+#define SDP_D_DST_BATCH_STRIDE_0_SECURE                                    (0x0)
+#define SDP_D_DST_BATCH_STRIDE_0_DUAL                                      (0x0)
+#define SDP_D_DST_BATCH_STRIDE_0_SCR                                         (0)
+#define SDP_D_DST_BATCH_STRIDE_0_WORD_COUNT                                (0x1)
+#define SDP_D_DST_BATCH_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BATCH_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BATCH_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_RANGE                   (31:5)
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_WOFFSET                  (0x0)
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DATA_FORMAT_0
+#define SDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xb0bc))
+#define SDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
+#define SDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
+#define SDP_D_DATA_FORMAT_0_SCR                                              (0)
+#define SDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
+#define SDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0xf))
+#define SDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_RANGE                           (1:0)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_WOFFSET                         (0x0)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
+
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT             (_MK_SHIFT_CONST(2))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_RANGE                            (3:2)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_WOFFSET                          (0x0)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_DEFAULT_MASK     (_MK_MASK_CONST(0x3))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8               (_MK_ENUM_CONST(0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16              (_MK_ENUM_CONST(1))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16               (_MK_ENUM_CONST(2))
+
+
+// Register SDP_D_CVT_OFFSET_0
+#define SDP_D_CVT_OFFSET_0                              (_MK_ADDR_CONST(0xb0c0))
+#define SDP_D_CVT_OFFSET_0_SECURE                                          (0x0)
+#define SDP_D_CVT_OFFSET_0_DUAL                                            (0x0)
+#define SDP_D_CVT_OFFSET_0_SCR                                               (0)
+#define SDP_D_CVT_OFFSET_0_WORD_COUNT                                      (0x1)
+#define SDP_D_CVT_OFFSET_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_RANGE                               (31:0)
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_WOFFSET                              (0x0)
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_CVT_SCALE_0
+#define SDP_D_CVT_SCALE_0                               (_MK_ADDR_CONST(0xb0c4))
+#define SDP_D_CVT_SCALE_0_SECURE                                           (0x0)
+#define SDP_D_CVT_SCALE_0_DUAL                                             (0x0)
+#define SDP_D_CVT_SCALE_0_SCR                                                (0)
+#define SDP_D_CVT_SCALE_0_WORD_COUNT                                       (0x1)
+#define SDP_D_CVT_SCALE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_RESET_MASK                    (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_READ_MASK                     (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_WRITE_MASK                    (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_RANGE                                 (15:0)
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_WOFFSET                                (0x0)
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_DEFAULT_MASK        (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_CVT_SHIFT_0
+#define SDP_D_CVT_SHIFT_0                               (_MK_ADDR_CONST(0xb0c8))
+#define SDP_D_CVT_SHIFT_0_SECURE                                           (0x0)
+#define SDP_D_CVT_SHIFT_0_DUAL                                             (0x0)
+#define SDP_D_CVT_SHIFT_0_SCR                                                (0)
+#define SDP_D_CVT_SHIFT_0_WORD_COUNT                                       (0x1)
+#define SDP_D_CVT_SHIFT_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_RESET_MASK                      (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_READ_MASK                       (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_WRITE_MASK                      (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_RANGE                                  (5:0)
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_WOFFSET                                (0x0)
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_DEFAULT_MASK          (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_0
+#define SDP_D_STATUS_0                                  (_MK_ADDR_CONST(0xb0cc))
+#define SDP_D_STATUS_0_SECURE                                              (0x0)
+#define SDP_D_STATUS_0_DUAL                                                (0x0)
+#define SDP_D_STATUS_0_SCR                                                   (0)
+#define SDP_D_STATUS_0_WORD_COUNT                                          (0x1)
+#define SDP_D_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_RESET_MASK                          (_MK_MASK_CONST(0x1))
+#define SDP_D_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_READ_MASK                           (_MK_MASK_CONST(0x1))
+#define SDP_D_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_RANGE                                (0:0)
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_WOFFSET                              (0x0)
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_NAN_INPUT_NUM_0
+#define SDP_D_STATUS_NAN_INPUT_NUM_0                    (_MK_ADDR_CONST(0xb0d0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SECURE                                (0x0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_DUAL                                  (0x0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SCR                                     (0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_WORD_COUNT                            (0x1)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_RANGE           (31:0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_WOFFSET          (0x0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_INF_INPUT_NUM_0
+#define SDP_D_STATUS_INF_INPUT_NUM_0                    (_MK_ADDR_CONST(0xb0d4))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SECURE                                (0x0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_DUAL                                  (0x0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SCR                                     (0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_WORD_COUNT                            (0x1)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_RANGE           (31:0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_WOFFSET          (0x0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0                   (_MK_ADDR_CONST(0xb0d8))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SECURE                               (0x0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_DUAL                                 (0x0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SCR                                    (0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_WORD_COUNT                           (0x1)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_RANGE         (31:0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_WOFFSET        (0x0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_ENABLE_0
+#define SDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xb0dc))
+#define SDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
+#define SDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
+#define SDP_D_PERF_ENABLE_0_SCR                                              (0)
+#define SDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
+#define SDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0xf))
+#define SDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_RANGE                              (0:0)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_WOFFSET                            (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_INIT_ENUM                           (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_RANGE                              (1:1)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_WOFFSET                            (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_INIT_ENUM                           (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT               (_MK_SHIFT_CONST(2))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_RANGE                              (2:2)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_WOFFSET                            (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_INIT_ENUM                           (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT     (_MK_SHIFT_CONST(3))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_RANGE                    (3:3)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_WOFFSET                  (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_INIT_ENUM                 (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO         (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES        (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_PERF_WDMA_WRITE_STALL_0
+#define SDP_D_PERF_WDMA_WRITE_STALL_0                   (_MK_ADDR_CONST(0xb0e0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SECURE                               (0x0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_DUAL                                 (0x0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SCR                                    (0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WORD_COUNT                           (0x1)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT      (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_RANGE                    (31:0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_WOFFSET                   (0x0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_UFLOW_0
+#define SDP_D_PERF_LUT_UFLOW_0                          (_MK_ADDR_CONST(0xb0e4))
+#define SDP_D_PERF_LUT_UFLOW_0_SECURE                                      (0x0)
+#define SDP_D_PERF_LUT_UFLOW_0_DUAL                                        (0x0)
+#define SDP_D_PERF_LUT_UFLOW_0_SCR                                           (0)
+#define SDP_D_PERF_LUT_UFLOW_0_WORD_COUNT                                  (0x1)
+#define SDP_D_PERF_LUT_UFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_UFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_RANGE                            (31:0)
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_WOFFSET                           (0x0)
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_OFLOW_0
+#define SDP_D_PERF_LUT_OFLOW_0                          (_MK_ADDR_CONST(0xb0e8))
+#define SDP_D_PERF_LUT_OFLOW_0_SECURE                                      (0x0)
+#define SDP_D_PERF_LUT_OFLOW_0_DUAL                                        (0x0)
+#define SDP_D_PERF_LUT_OFLOW_0_SCR                                           (0)
+#define SDP_D_PERF_LUT_OFLOW_0_WORD_COUNT                                  (0x1)
+#define SDP_D_PERF_LUT_OFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_OFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_RANGE                            (31:0)
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_WOFFSET                           (0x0)
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_OUT_SATURATION_0
+#define SDP_D_PERF_OUT_SATURATION_0                     (_MK_ADDR_CONST(0xb0ec))
+#define SDP_D_PERF_OUT_SATURATION_0_SECURE                                 (0x0)
+#define SDP_D_PERF_OUT_SATURATION_0_DUAL                                   (0x0)
+#define SDP_D_PERF_OUT_SATURATION_0_SCR                                      (0)
+#define SDP_D_PERF_OUT_SATURATION_0_WORD_COUNT                             (0x1)
+#define SDP_D_PERF_OUT_SATURATION_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_OUT_SATURATION_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_OUT_SATURATION_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_RANGE                  (31:0)
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_WOFFSET                 (0x0)
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_HYBRID_0
+#define SDP_D_PERF_LUT_HYBRID_0                         (_MK_ADDR_CONST(0xb0f0))
+#define SDP_D_PERF_LUT_HYBRID_0_SECURE                                     (0x0)
+#define SDP_D_PERF_LUT_HYBRID_0_DUAL                                       (0x0)
+#define SDP_D_PERF_LUT_HYBRID_0_SCR                                          (0)
+#define SDP_D_PERF_LUT_HYBRID_0_WORD_COUNT                                 (0x1)
+#define SDP_D_PERF_LUT_HYBRID_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_HYBRID_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_RANGE                          (31:0)
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_WOFFSET                         (0x0)
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_LE_HIT_0
+#define SDP_D_PERF_LUT_LE_HIT_0                         (_MK_ADDR_CONST(0xb0f4))
+#define SDP_D_PERF_LUT_LE_HIT_0_SECURE                                     (0x0)
+#define SDP_D_PERF_LUT_LE_HIT_0_DUAL                                       (0x0)
+#define SDP_D_PERF_LUT_LE_HIT_0_SCR                                          (0)
+#define SDP_D_PERF_LUT_LE_HIT_0_WORD_COUNT                                 (0x1)
+#define SDP_D_PERF_LUT_LE_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LE_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_RANGE                          (31:0)
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_WOFFSET                         (0x0)
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_LO_HIT_0
+#define SDP_D_PERF_LUT_LO_HIT_0                         (_MK_ADDR_CONST(0xb0f8))
+#define SDP_D_PERF_LUT_LO_HIT_0_SECURE                                     (0x0)
+#define SDP_D_PERF_LUT_LO_HIT_0_DUAL                                       (0x0)
+#define SDP_D_PERF_LUT_LO_HIT_0_SCR                                          (0)
+#define SDP_D_PERF_LUT_LO_HIT_0_WORD_COUNT                                 (0x1)
+#define SDP_D_PERF_LUT_LO_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LO_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_RANGE                          (31:0)
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_WOFFSET                         (0x0)
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_S_STATUS_0
+#define PDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xc000))
+#define PDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
+#define PDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
+#define PDP_RDMA_S_STATUS_0_SCR                                              (0)
+#define PDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
+#define PDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
+#define PDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
+#define PDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
+
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
+
+
+// Register PDP_RDMA_S_POINTER_0
+#define PDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xc004))
+#define PDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
+#define PDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
+#define PDP_RDMA_S_POINTER_0_SCR                                             (0)
+#define PDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
+#define PDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define PDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define PDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
+
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_OP_ENABLE_0
+#define PDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xc008))
+#define PDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
+#define PDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
+#define PDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0                 (_MK_ADDR_CONST(0xc00c))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SECURE                             (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_DUAL                               (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SCR                                  (0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_RESET_MASK      (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_READ_MASK       (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_WRITE_MASK      (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_RANGE               (12:0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_WOFFSET              (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0                (_MK_ADDR_CONST(0xc010))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SECURE                            (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_DUAL                              (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SCR                                 (0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_WORD_COUNT                        (0x1)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_RESET_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_RESET_MASK     (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_VAL    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_READ_MASK      (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_WRITE_MASK     (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_RANGE             (12:0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_WOFFSET            (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0               (_MK_ADDR_CONST(0xc014))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SECURE                           (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_DUAL                             (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SCR                                (0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_WORD_COUNT                       (0x1)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_RESET_MASK    (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_READ_MASK     (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_WRITE_MASK    (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_RANGE           (12:0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_WOFFSET          (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_FLYING_MODE_0
+#define PDP_RDMA_D_FLYING_MODE_0                        (_MK_ADDR_CONST(0xc018))
+#define PDP_RDMA_D_FLYING_MODE_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_SCR                                         (0)
+#define PDP_RDMA_D_FLYING_MODE_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_FLYING_MODE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT          (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_RANGE                         (0:0)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_WOFFSET                       (0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING       (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING      (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xc01c))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xc020))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_LINE_STRIDE_0
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xc024))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xc028))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_RAM_CFG_0
+#define PDP_RDMA_D_SRC_RAM_CFG_0                        (_MK_ADDR_CONST(0xc02c))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SCR                                         (0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_DATA_FORMAT_0
+#define PDP_RDMA_D_DATA_FORMAT_0                        (_MK_ADDR_CONST(0xc030))
+#define PDP_RDMA_D_DATA_FORMAT_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_SCR                                         (0)
+#define PDP_RDMA_D_DATA_FORMAT_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_DATA_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT           (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_RANGE                          (1:0)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                        (0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8             (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16            (_MK_ENUM_CONST(1))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16             (_MK_ENUM_CONST(2))
+
+
+// Register PDP_RDMA_D_OPERATION_MODE_CFG_0
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0                 (_MK_ADDR_CONST(0xc034))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SECURE                             (0x0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_DUAL                               (0x0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SCR                                  (0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_READ_MASK         (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT     (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_RANGE                    (7:0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_WOFFSET                  (0x0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0                 (_MK_ADDR_CONST(0xc038))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SECURE                             (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_DUAL                               (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SCR                                  (0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_READ_MASK         (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_RANGE                 (3:0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_WOFFSET               (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 \
+	(_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 \
+	(_MK_ENUM_CONST(1))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 \
+	(_MK_ENUM_CONST(2))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 \
+	(_MK_ENUM_CONST(3))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 \
+	(_MK_ENUM_CONST(4))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 \
+	(_MK_ENUM_CONST(5))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 \
+	(_MK_ENUM_CONST(6))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 \
+	(_MK_ENUM_CONST(7))
+
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(4))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_RANGE          (7:4)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_WOFFSET        (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_POOLING_PADDING_CFG_0
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0                (_MK_ADDR_CONST(0xc03c))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SECURE                            (0x0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_DUAL                              (0x0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SCR                                 (0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_WORD_COUNT                        (0x1)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_RESET_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SW_DEFAULT_VAL    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_READ_MASK         (_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT    (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_RANGE                   (3:0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_WOFFSET                 (0x0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0                   (_MK_ADDR_CONST(0xc040))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SECURE                               (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_DUAL                                 (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SCR                                    (0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_WORD_COUNT                           (0x1)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_RESET_MASK    (_MK_MASK_CONST(0x3fffffff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_READ_MASK     (_MK_MASK_CONST(0x3fffffff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_WRITE_MASK    (_MK_MASK_CONST(0x3fffffff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_RANGE         (9:0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_WOFFSET       (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT \
+	(_MK_SHIFT_CONST(10))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_RANGE        (19:10)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_WOFFSET        (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_RANGE         (29:20)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_WOFFSET         (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_PERF_ENABLE_0
+#define PDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xc044))
+#define PDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
+#define PDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                              (0:0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                            (0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                      (DISABLE)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE              (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE               (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_PERF_READ_STALL_0
+#define PDP_RDMA_D_PERF_READ_STALL_0                    (_MK_ADDR_CONST(0xc048))
+#define PDP_RDMA_D_PERF_READ_STALL_0_SECURE                                (0x0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_DUAL                                  (0x0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_SCR                                     (0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_WORD_COUNT                            (0x1)
+#define PDP_RDMA_D_PERF_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_PERF_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_RANGE                (31:0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_WOFFSET               (0x0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_CYA_0
+#define PDP_RDMA_D_CYA_0                                (_MK_ADDR_CONST(0xc04c))
+#define PDP_RDMA_D_CYA_0_SECURE                                            (0x0)
+#define PDP_RDMA_D_CYA_0_DUAL                                              (0x0)
+#define PDP_RDMA_D_CYA_0_SCR                                                 (0)
+#define PDP_RDMA_D_CYA_0_WORD_COUNT                                        (0x1)
+#define PDP_RDMA_D_CYA_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_RESET_MASK                 (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_READ_MASK                  (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_WRITE_MASK                 (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_CYA_SHIFT                          (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT))
+#define PDP_RDMA_D_CYA_0_CYA_RANGE                                        (31:0)
+#define PDP_RDMA_D_CYA_0_CYA_WOFFSET                                       (0x0)
+#define PDP_RDMA_D_CYA_0_CYA_DEFAULT                       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_CYA_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
+
+
+// Register PDP_S_STATUS_0
+#define PDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xd000))
+#define PDP_S_STATUS_0_SECURE                                              (0x0)
+#define PDP_S_STATUS_0_DUAL                                                (0x0)
+#define PDP_S_STATUS_0_SCR                                                   (0)
+#define PDP_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define PDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define PDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define PDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define PDP_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT))
+#define PDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define PDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define PDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define PDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define PDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define PDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define PDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define PDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define PDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define PDP_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT))
+#define PDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define PDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define PDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define PDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define PDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define PDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define PDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define PDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register PDP_S_POINTER_0
+#define PDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xd004))
+#define PDP_S_POINTER_0_SECURE                                             (0x0)
+#define PDP_S_POINTER_0_DUAL                                               (0x0)
+#define PDP_S_POINTER_0_SCR                                                  (0)
+#define PDP_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define PDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define PDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define PDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define PDP_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT))
+#define PDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define PDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define PDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define PDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define PDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define PDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define PDP_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT))
+#define PDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define PDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define PDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define PDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define PDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_OP_ENABLE_0
+#define PDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xd008))
+#define PDP_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define PDP_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define PDP_D_OP_ENABLE_0_SCR                                                (0)
+#define PDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define PDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define PDP_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define PDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define PDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define PDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_DATA_CUBE_IN_WIDTH_0
+#define PDP_D_DATA_CUBE_IN_WIDTH_0                      (_MK_ADDR_CONST(0xd00c))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SECURE                                  (0x0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_DUAL                                    (0x0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SCR                                       (0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_WORD_COUNT                              (0x1)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_RESET_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_READ_MASK            (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT      (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_RANGE                    (12:0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_WOFFSET                   (0x0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_IN_HEIGHT_0
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0                     (_MK_ADDR_CONST(0xd010))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SECURE                                 (0x0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_DUAL                                   (0x0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SCR                                      (0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_WORD_COUNT                             (0x1)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_RESET_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_READ_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT    (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_RANGE                  (12:0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_WOFFSET                 (0x0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_IN_CHANNEL_0
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0                    (_MK_ADDR_CONST(0xd014))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SECURE                                (0x0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_DUAL                                  (0x0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SCR                                     (0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_WORD_COUNT                            (0x1)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_RANGE                (12:0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_WOFFSET               (0x0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_OUT_WIDTH_0
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0                     (_MK_ADDR_CONST(0xd018))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SECURE                                 (0x0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_DUAL                                   (0x0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SCR                                      (0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_WORD_COUNT                             (0x1)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_RESET_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_READ_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT    (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_RANGE                  (12:0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_WOFFSET                 (0x0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0                    (_MK_ADDR_CONST(0xd01c))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SECURE                                (0x0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_DUAL                                  (0x0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SCR                                     (0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_WORD_COUNT                            (0x1)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_RANGE                (12:0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_WOFFSET               (0x0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0                   (_MK_ADDR_CONST(0xd020))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SECURE                               (0x0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_DUAL                                 (0x0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SCR                                    (0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_WORD_COUNT                           (0x1)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_RANGE              (12:0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_WOFFSET             (0x0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_OPERATION_MODE_CFG_0
+#define PDP_D_OPERATION_MODE_CFG_0                      (_MK_ADDR_CONST(0xd024))
+#define PDP_D_OPERATION_MODE_CFG_0_SECURE                                  (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_DUAL                                    (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_SCR                                       (0)
+#define PDP_D_OPERATION_MODE_CFG_0_WORD_COUNT                              (0x1)
+#define PDP_D_OPERATION_MODE_CFG_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_RESET_MASK           (_MK_MASK_CONST(0xff13))
+#define PDP_D_OPERATION_MODE_CFG_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_READ_MASK            (_MK_MASK_CONST(0xff13))
+#define PDP_D_OPERATION_MODE_CFG_0_WRITE_MASK           (_MK_MASK_CONST(0xff13))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT     (_MK_SHIFT_CONST(0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_RANGE                    (1:0)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_WOFFSET                  (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE \
+	(_MK_ENUM_CONST(0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX \
+	(_MK_ENUM_CONST(1))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN \
+	(_MK_ENUM_CONST(2))
+
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_RANGE                       (4:4)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_WOFFSET                     (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING     (_MK_ENUM_CONST(0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING    (_MK_ENUM_CONST(1))
+
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT          (_MK_SHIFT_CONST(8))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_RANGE                        (15:8)
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_WOFFSET                       (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT       (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_NAN_FLUSH_TO_ZERO_0
+#define PDP_D_NAN_FLUSH_TO_ZERO_0                       (_MK_ADDR_CONST(0xd028))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SECURE                                   (0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_DUAL                                     (0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SCR                                        (0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                               (0x1)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK               (_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_READ_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK               (_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT         (_MK_SHIFT_CONST(0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                        (0:0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                      (0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM                (DISABLE)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE        (_MK_ENUM_CONST(0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE         (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_PARTIAL_WIDTH_IN_0
+#define PDP_D_PARTIAL_WIDTH_IN_0                        (_MK_ADDR_CONST(0xd02c))
+#define PDP_D_PARTIAL_WIDTH_IN_0_SECURE                                    (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_DUAL                                      (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_SCR                                         (0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_WORD_COUNT                                (0x1)
+#define PDP_D_PARTIAL_WIDTH_IN_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_RESET_MASK         (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_READ_MASK          (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_WRITE_MASK         (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_RANGE              (9:0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_WOFFSET            (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT \
+	(_MK_SHIFT_CONST(10))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_RANGE             (19:10)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_WOFFSET             (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_RANGE              (29:20)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_WOFFSET              (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_PARTIAL_WIDTH_OUT_0
+#define PDP_D_PARTIAL_WIDTH_OUT_0                       (_MK_ADDR_CONST(0xd030))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SECURE                                   (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_DUAL                                     (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SCR                                        (0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_WORD_COUNT                               (0x1)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_RESET_MASK        (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_READ_MASK         (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_WRITE_MASK        (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_RANGE            (9:0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_WOFFSET          (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT \
+	(_MK_SHIFT_CONST(10))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_RANGE           (19:10)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_WOFFSET           (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_RANGE            (29:20)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_WOFFSET            (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_KERNEL_CFG_0
+#define PDP_D_POOLING_KERNEL_CFG_0                      (_MK_ADDR_CONST(0xd034))
+#define PDP_D_POOLING_KERNEL_CFG_0_SECURE                                  (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_DUAL                                    (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_SCR                                       (0)
+#define PDP_D_POOLING_KERNEL_CFG_0_WORD_COUNT                              (0x1)
+#define PDP_D_POOLING_KERNEL_CFG_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_RESET_MASK         (_MK_MASK_CONST(0xff0f0f))
+#define PDP_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_READ_MASK          (_MK_MASK_CONST(0xff0f0f))
+#define PDP_D_POOLING_KERNEL_CFG_0_WRITE_MASK         (_MK_MASK_CONST(0xff0f0f))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT       (_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_RANGE                      (3:0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_WOFFSET                    (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 \
+	(_MK_ENUM_CONST(0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 \
+	(_MK_ENUM_CONST(1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 \
+	(_MK_ENUM_CONST(2))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 \
+	(_MK_ENUM_CONST(3))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 \
+	(_MK_ENUM_CONST(4))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 \
+	(_MK_ENUM_CONST(5))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 \
+	(_MK_ENUM_CONST(6))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 \
+	(_MK_ENUM_CONST(7))
+
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT      (_MK_SHIFT_CONST(8))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_RANGE                    (11:8)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_WOFFSET                   (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1 \
+	(_MK_ENUM_CONST(0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2 \
+	(_MK_ENUM_CONST(1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3 \
+	(_MK_ENUM_CONST(2))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4 \
+	(_MK_ENUM_CONST(3))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5 \
+	(_MK_ENUM_CONST(4))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6 \
+	(_MK_ENUM_CONST(5))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7 \
+	(_MK_ENUM_CONST(6))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8 \
+	(_MK_ENUM_CONST(7))
+
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_RANGE             (19:16)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_WOFFSET             (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_RANGE            (23:20)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_WOFFSET            (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_RECIP_KERNEL_WIDTH_0
+#define PDP_D_RECIP_KERNEL_WIDTH_0                      (_MK_ADDR_CONST(0xd038))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SECURE                                  (0x0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_DUAL                                    (0x0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SCR                                       (0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_WORD_COUNT                              (0x1)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RESET_MASK          (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_READ_MASK           (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_WRITE_MASK          (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1ffff, \
+	PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_RANGE               (16:0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_WOFFSET              (0x0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_RECIP_KERNEL_HEIGHT_0
+#define PDP_D_RECIP_KERNEL_HEIGHT_0                     (_MK_ADDR_CONST(0xd03c))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SECURE                                 (0x0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_DUAL                                   (0x0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SCR                                      (0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_WORD_COUNT                             (0x1)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RESET_MASK         (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_READ_MASK          (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_WRITE_MASK         (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1ffff, \
+	PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_RANGE             (16:0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_WOFFSET            (0x0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_CFG_0
+#define PDP_D_POOLING_PADDING_CFG_0                     (_MK_ADDR_CONST(0xd040))
+#define PDP_D_POOLING_PADDING_CFG_0_SECURE                                 (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_DUAL                                   (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_SCR                                      (0)
+#define PDP_D_POOLING_PADDING_CFG_0_WORD_COUNT                             (0x1)
+#define PDP_D_POOLING_PADDING_CFG_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_RESET_MASK          (_MK_MASK_CONST(0x7777))
+#define PDP_D_POOLING_PADDING_CFG_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_READ_MASK           (_MK_MASK_CONST(0x7777))
+#define PDP_D_POOLING_PADDING_CFG_0_WRITE_MASK          (_MK_MASK_CONST(0x7777))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT          (_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_RANGE                         (2:0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_WOFFSET                       (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT           (_MK_SHIFT_CONST(4))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_RANGE                          (6:4)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_WOFFSET                        (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT         (_MK_SHIFT_CONST(8))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_RANGE                       (10:8)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_WOFFSET                      (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT       (_MK_SHIFT_CONST(12))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_RANGE                     (14:12)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_WOFFSET                     (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0             (_MK_ADDR_CONST(0xd044))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0             (_MK_ADDR_CONST(0xd048))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0             (_MK_ADDR_CONST(0xd04c))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0             (_MK_ADDR_CONST(0xd050))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0             (_MK_ADDR_CONST(0xd054))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0             (_MK_ADDR_CONST(0xd058))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0             (_MK_ADDR_CONST(0xd05c))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_BASE_ADDR_LOW_0
+#define PDP_D_SRC_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xd060))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SCR                                        (0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE                 (31:5)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_BASE_ADDR_HIGH_0
+#define PDP_D_SRC_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xd064))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE               (31:0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_LINE_STRIDE_0
+#define PDP_D_SRC_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xd068))
+#define PDP_D_SRC_LINE_STRIDE_0_SECURE                                     (0x0)
+#define PDP_D_SRC_LINE_STRIDE_0_DUAL                                       (0x0)
+#define PDP_D_SRC_LINE_STRIDE_0_SCR                                          (0)
+#define PDP_D_SRC_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define PDP_D_SRC_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                     (31:5)
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET                    (0x0)
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_SURFACE_STRIDE_0
+#define PDP_D_SRC_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xd06c))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SCR                                       (0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define PDP_D_SRC_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE               (31:5)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET              (0x0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_BASE_ADDR_LOW_0
+#define PDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xd070))
+#define PDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define PDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_BASE_ADDR_HIGH_0
+#define PDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xd074))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_LINE_STRIDE_0
+#define PDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xd078))
+#define PDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
+#define PDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
+#define PDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
+#define PDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define PDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_SURFACE_STRIDE_0
+#define PDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xd07c))
+#define PDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define PDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define PDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
+#define PDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define PDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_RAM_CFG_0
+#define PDP_D_DST_RAM_CFG_0                             (_MK_ADDR_CONST(0xd080))
+#define PDP_D_DST_RAM_CFG_0_SECURE                                         (0x0)
+#define PDP_D_DST_RAM_CFG_0_DUAL                                           (0x0)
+#define PDP_D_DST_RAM_CFG_0_SCR                                              (0)
+#define PDP_D_DST_RAM_CFG_0_WORD_COUNT                                     (0x1)
+#define PDP_D_DST_RAM_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_DATA_FORMAT_0
+#define PDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xd084))
+#define PDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
+#define PDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
+#define PDP_D_DATA_FORMAT_0_SCR                                              (0)
+#define PDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
+#define PDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT                (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_RANGE                               (1:0)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                             (0x0)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT             (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK        (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8                  (_MK_ENUM_CONST(0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16                 (_MK_ENUM_CONST(1))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16                  (_MK_ENUM_CONST(2))
+
+
+// Register PDP_D_INF_INPUT_NUM_0
+#define PDP_D_INF_INPUT_NUM_0                           (_MK_ADDR_CONST(0xd088))
+#define PDP_D_INF_INPUT_NUM_0_SECURE                                       (0x0)
+#define PDP_D_INF_INPUT_NUM_0_DUAL                                         (0x0)
+#define PDP_D_INF_INPUT_NUM_0_SCR                                            (0)
+#define PDP_D_INF_INPUT_NUM_0_WORD_COUNT                                   (0x1)
+#define PDP_D_INF_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_INF_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_INF_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_RANGE                         (31:0)
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_WOFFSET                        (0x0)
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_NAN_INPUT_NUM_0
+#define PDP_D_NAN_INPUT_NUM_0                           (_MK_ADDR_CONST(0xd08c))
+#define PDP_D_NAN_INPUT_NUM_0_SECURE                                       (0x0)
+#define PDP_D_NAN_INPUT_NUM_0_DUAL                                         (0x0)
+#define PDP_D_NAN_INPUT_NUM_0_SCR                                            (0)
+#define PDP_D_NAN_INPUT_NUM_0_WORD_COUNT                                   (0x1)
+#define PDP_D_NAN_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_RANGE                         (31:0)
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_WOFFSET                        (0x0)
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_NAN_OUTPUT_NUM_0
+#define PDP_D_NAN_OUTPUT_NUM_0                          (_MK_ADDR_CONST(0xd090))
+#define PDP_D_NAN_OUTPUT_NUM_0_SECURE                                      (0x0)
+#define PDP_D_NAN_OUTPUT_NUM_0_DUAL                                        (0x0)
+#define PDP_D_NAN_OUTPUT_NUM_0_SCR                                           (0)
+#define PDP_D_NAN_OUTPUT_NUM_0_WORD_COUNT                                  (0x1)
+#define PDP_D_NAN_OUTPUT_NUM_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_OUTPUT_NUM_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT         (_MK_SHIFT_CONST(0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_RANGE                       (31:0)
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_WOFFSET                      (0x0)
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_PERF_ENABLE_0
+#define PDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xd094))
+#define PDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
+#define PDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
+#define PDP_D_PERF_ENABLE_0_SCR                                              (0)
+#define PDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
+#define PDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_RANGE                                   (0:0)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                 (0x0)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                           (DISABLE)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_PERF_WRITE_STALL_0
+#define PDP_D_PERF_WRITE_STALL_0                        (_MK_ADDR_CONST(0xd098))
+#define PDP_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
+#define PDP_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
+#define PDP_D_PERF_WRITE_STALL_0_SCR                                         (0)
+#define PDP_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
+#define PDP_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT     (_MK_SHIFT_CONST(0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_RANGE                   (31:0)
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_WOFFSET                  (0x0)
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_CYA_0
+#define PDP_D_CYA_0                                     (_MK_ADDR_CONST(0xd09c))
+#define PDP_D_CYA_0_SECURE                                                 (0x0)
+#define PDP_D_CYA_0_DUAL                                                   (0x0)
+#define PDP_D_CYA_0_SCR                                                      (0)
+#define PDP_D_CYA_0_WORD_COUNT                                             (0x1)
+#define PDP_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
+#define PDP_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT))
+#define PDP_D_CYA_0_CYA_RANGE                                             (31:0)
+#define PDP_D_CYA_0_CYA_WOFFSET                                            (0x0)
+#define PDP_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_S_STATUS_0
+#define CDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xe000))
+#define CDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
+#define CDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
+#define CDP_RDMA_S_STATUS_0_SCR                                              (0)
+#define CDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
+#define CDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
+#define CDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
+#define CDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
+
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
+
+
+// Register CDP_RDMA_S_POINTER_0
+#define CDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xe004))
+#define CDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
+#define CDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
+#define CDP_RDMA_S_POINTER_0_SCR                                             (0)
+#define CDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
+#define CDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define CDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define CDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
+
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_OP_ENABLE_0
+#define CDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xe008))
+#define CDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
+#define CDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
+#define CDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0                    (_MK_ADDR_CONST(0xe00c))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SECURE                                (0x0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_DUAL                                  (0x0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SCR                                     (0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WORD_COUNT                            (0x1)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                          (12:0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                         (0x0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0                   (_MK_ADDR_CONST(0xe010))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SECURE                               (0x0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_DUAL                                 (0x0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SCR                                    (0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                           (0x1)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                        (12:0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                       (0x0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0                  (_MK_ADDR_CONST(0xe014))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SECURE                              (0x0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_DUAL                                (0x0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SCR                                   (0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                          (0x1)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_MASK       (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_READ_MASK        (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                      (12:0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                     (0x0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xe018))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xe01c))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_LINE_STRIDE_0
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xe020))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xe024))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_DMA_CFG_0
+#define CDP_RDMA_D_SRC_DMA_CFG_0                        (_MK_ADDR_CONST(0xe028))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SECURE                                    (0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_DUAL                                      (0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SCR                                         (0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_WORD_COUNT                                (0x1)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0                 (_MK_ADDR_CONST(0xe02c))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SECURE                             (0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_DUAL                               (0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SCR                                  (0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_WORD_COUNT                         (0x1)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_RESET_MASK         (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_READ_MASK          (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_WRITE_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_RANGE           (0:0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_WOFFSET         (0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE \
+	(_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE \
+	(_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_OPERATION_MODE_0
+#define CDP_RDMA_D_OPERATION_MODE_0                     (_MK_ADDR_CONST(0xe030))
+#define CDP_RDMA_D_OPERATION_MODE_0_SECURE                                 (0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_DUAL                                   (0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_SCR                                      (0)
+#define CDP_RDMA_D_OPERATION_MODE_0_WORD_COUNT                             (0x1)
+#define CDP_RDMA_D_OPERATION_MODE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_RESET_MASK             (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_OPERATION_MODE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_READ_MASK              (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_OPERATION_MODE_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT    (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_RANGE                   (1:0)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WOFFSET                 (0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE \
+	(_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE \
+	(_MK_ENUM_CONST(1))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY \
+	(_MK_ENUM_CONST(2))
+
+
+// Register CDP_RDMA_D_DATA_FORMAT_0
+#define CDP_RDMA_D_DATA_FORMAT_0                        (_MK_ADDR_CONST(0xe034))
+#define CDP_RDMA_D_DATA_FORMAT_0_SECURE                                    (0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_DUAL                                      (0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_SCR                                         (0)
+#define CDP_RDMA_D_DATA_FORMAT_0_WORD_COUNT                                (0x1)
+#define CDP_RDMA_D_DATA_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_RANGE                          (1:0)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                        (0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8             (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16            (_MK_ENUM_CONST(1))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16             (_MK_ENUM_CONST(2))
+
+
+// Register CDP_RDMA_D_PERF_ENABLE_0
+#define CDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xe038))
+#define CDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
+#define CDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
+#define CDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                              (0:0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                            (0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                      (DISABLE)
+#define CDP_RDM