author: Andy Hu <andy.hu@starfivetech.com> 2023-10-18 20:13:37 +0800
committer: Andy Hu <andy.hu@starfivetech.com> 2023-10-18 20:13:37 +0800
commit: fd7482e454293064b658ae439baa0b098e25799d
parent: 93c3fa8705590822c0cff01a7e4e64975bef5ab2
Commit Summary:
Diffstat:
2 files changed, 30 insertions, 24 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 054997b44290..5c8485ea8859 100755
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -752,3 +752,36 @@
memory-region = <&hifi4_reserved>;
status = "disabled";
};
+
+&qspi {
+ nor_flash: nor-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ cdns,read-delay = <5>;
+ spi-max-frequency = <100000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0x40000>;
+ };
+ uboot-env@100000 {
+ reg = <0xf0000 0x10000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0x300000>;
+ };
+ data@f00000 {
+ reg = <0xf00000 0x100000>;
+ };
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index e5d0445767f1..134a2c1c8df5 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -404,33 +404,6 @@
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
spi-max-frequency = <250000000>;
-
- nor_flash: nor-flash@0 {
- compatible = "jedec,spi-nor";
- reg=<0>;
- cdns,read-delay = <5>;
- spi-max-frequency = <100000000>;
- cdns,tshsl-ns = <1>;
- cdns,tsd2d-ns = <1>;
- cdns,tchsh-ns = <1>;
- cdns,tslch-ns = <1>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- spl@0 {
- reg = <0x0 0x40000>;
- };
- uboot@100000 {
- reg = <0x100000 0x300000>;
- };
- data@f00000 {
- reg = <0xf00000 0x100000>;
- };
- };
- };
};
otp: otp@17050000 {