VisionFive2 Linux kernel

StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

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b24413180f560 (Greg Kroah-Hartman 2017-11-01 15:07:57 +0100  1) // SPDX-License-Identifier: GPL-2.0
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  2) /*
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  3)  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  4)  * Derived from fixup.c of i386 tree.
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  5)  */
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  6) 
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  7) #include <linux/pci.h>
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900  8) #include <linux/init.h>
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700  9) #include <linux/vgaarb.h>
20cde694027e7 (Bruno Prémont      2014-06-25 00:55:01 +0200 10) #include <linux/screen_info.h>
df41017eafd26 (Christoph Hellwig  2019-08-13 09:25:12 +0200 11) #include <asm/uv/uv.h>
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 12) 
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 13) /*
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 14)  * Fixup to mark boot BIOS video selected by BIOS before it changes
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 15)  *
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 16)  * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 17)  *
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 18)  * The standard boot ROM sequence for an x86 machine uses the BIOS
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 19)  * to select an initial video card for boot display. This boot video
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 20)  * card will have its BIOS copied to 0xC0000 in system RAM.
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 21)  * IORESOURCE_ROM_SHADOW is used to associate the boot video
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 22)  * card with this copy. On laptops this copy has to be used since
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 23)  * the main ROM may be compressed or combined with another image.
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 24)  * See pci_map_rom() for use of this flag. Before marking the device
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 25)  * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 26)  * by either arch code or vga-arbitration; if so only apply the fixup to this
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 27)  * already-determined primary video card.
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 28)  */
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 29) 
5b5e76e9cb294 (Greg Kroah-Hartman 2012-12-21 14:05:13 -0800 30) static void pci_fixup_video(struct pci_dev *pdev)
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 31) {
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 32) 	struct pci_dev *bridge;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 33) 	struct pci_bus *bus;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 34) 	u16 config;
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 35) 	struct resource *res;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 36) 
df41017eafd26 (Christoph Hellwig  2019-08-13 09:25:12 +0200 37) 	if (is_uv_system())
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 38) 		return;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 39) 	/* Maybe, this machine supports legacy memory map. */
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 40) 
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 41) 	/* Is VGA routed to us? */
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 42) 	bus = pdev->bus;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 43) 	while (bus) {
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 44) 		bridge = bus->self;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 45) 
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 46) 		/*
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 47) 		 * From information provided by
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 48) 		 * "David Miller" <davem@davemloft.net>
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 49) 		 * The bridge control register is valid for PCI header
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 50) 		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 51) 		 * PCI header type NORMAL.
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 52) 		 */
11a3bd095cb1a (Yijing Wang        2014-05-04 12:23:40 +0800 53) 		if (bridge && (pci_is_bridge(bridge))) {
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 54) 			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 55) 						&config);
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 56) 			if (!(config & PCI_BRIDGE_CTL_VGA))
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 57) 				return;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 58) 		}
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 59) 		bus = bus->parent;
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 60) 	}
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 61) 	if (!vga_default_device() || pdev == vga_default_device()) {
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 62) 		pci_read_config_word(pdev, PCI_COMMAND, &config);
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 63) 		if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 64) 			res = &pdev->resource[PCI_ROM_RESOURCE];
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 65) 
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 66) 			pci_disable_rom(pdev);
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 67) 			if (res->parent)
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 68) 				release_resource(res);
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 69) 
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 70) 			res->start = 0xC0000;
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 71) 			res->end = res->start + 0x20000 - 1;
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 72) 			res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 73) 				     IORESOURCE_PCI_FIXED;
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 74) 			dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
0c0e0736acad4 (Bjorn Helgaas      2016-03-01 11:38:46 -0600 75) 				 res);
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 76) 		}
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 77) 	}
6b5c76b8e2ff2 (Eiichiro Oiwa      2006-10-23 15:14:07 +0900 78) }
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 79) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
058a2e1bb065f (Sander Eikelenboom 2014-02-14 11:55:13 -0700 80) 				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);