ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 1) /*
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 2) * Copyright © 2016 Intel Corporation
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 3) *
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 5) * copy of this software and associated documentation files (the "Software"),
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 6) * to deal in the Software without restriction, including without limitation
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 9) * Software is furnished to do so, subject to the following conditions:
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 10) *
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 11) * The above copyright notice and this permission notice shall be included in
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 12) * all copies or substantial portions of the Software.
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 13) *
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 14) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 15) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 16) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 17) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 18) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 19) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 20) * OTHER DEALINGS IN THE SOFTWARE.
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 21) */
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 22)
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 23) #ifndef DRM_DP_DUAL_MODE_HELPER_H
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 24) #define DRM_DP_DUAL_MODE_HELPER_H
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 25)
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 26) #include <linux/types.h>
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 27)
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 28) /*
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 29) * Optional for type 1 DVI adaptors
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 30) * Mandatory for type 1 HDMI and type 2 adaptors
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 31) */
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 32) #define DP_DUAL_MODE_HDMI_ID 0x00 /* 00-0f */
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 33) #define DP_DUAL_MODE_HDMI_ID_LEN 16
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 34) /*
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 35) * Optional for type 1 adaptors
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 36) * Mandatory for type 2 adaptors
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 37) */
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 38) #define DP_DUAL_MODE_ADAPTOR_ID 0x10
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 39) #define DP_DUAL_MODE_REV_MASK 0x07
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 40) #define DP_DUAL_MODE_REV_TYPE2 0x00
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 41) #define DP_DUAL_MODE_TYPE_MASK 0xf0
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 42) #define DP_DUAL_MODE_TYPE_TYPE2 0xa0
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 43) /* This field is marked reserved in dual mode spec, used in LSPCON */
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 44) #define DP_DUAL_MODE_TYPE_HAS_DPCD 0x08
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 45) #define DP_DUAL_MODE_IEEE_OUI 0x11 /* 11-13*/
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 46) #define DP_DUAL_IEEE_OUI_LEN 3
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 47) #define DP_DUAL_DEVICE_ID 0x14 /* 14-19 */
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 48) #define DP_DUAL_DEVICE_ID_LEN 6
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 49) #define DP_DUAL_MODE_HARDWARE_REV 0x1a
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 50) #define DP_DUAL_MODE_FIRMWARE_MAJOR_REV 0x1b
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 51) #define DP_DUAL_MODE_FIRMWARE_MINOR_REV 0x1c
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 52) #define DP_DUAL_MODE_MAX_TMDS_CLOCK 0x1d
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 53) #define DP_DUAL_MODE_I2C_SPEED_CAP 0x1e
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 54) #define DP_DUAL_MODE_TMDS_OEN 0x20
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 55) #define DP_DUAL_MODE_TMDS_DISABLE 0x01
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 56) #define DP_DUAL_MODE_HDMI_PIN_CTRL 0x21
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 57) #define DP_DUAL_MODE_CEC_ENABLE 0x01
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 58) #define DP_DUAL_MODE_I2C_SPEED_CTRL 0x22
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 59)
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 60) /* LSPCON specific registers, defined by MCA */
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 61) #define DP_DUAL_MODE_LSPCON_MODE_CHANGE 0x40
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 62) #define DP_DUAL_MODE_LSPCON_CURRENT_MODE 0x41
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 63) #define DP_DUAL_MODE_LSPCON_MODE_PCON 0x1
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 64)
92ea222015f17 (Lyude Paul 2021-04-23 14:43:00 -0400 65) struct drm_device;
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 66) struct i2c_adapter;
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 67)
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 68) ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 69) u8 offset, void *buffer, size_t size);
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 70) ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 71) u8 offset, const void *buffer, size_t size);
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 72)
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 73) /**
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 74) * enum drm_lspcon_mode
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 75) * @DRM_LSPCON_MODE_INVALID: No LSPCON.
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 76) * @DRM_LSPCON_MODE_LS: Level shifter mode of LSPCON
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 77) * which drives DP++ to HDMI 1.4 conversion.
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 78) * @DRM_LSPCON_MODE_PCON: Protocol converter mode of LSPCON
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 79) * which drives DP++ to HDMI 2.0 active conversion.
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 80) */
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 81) enum drm_lspcon_mode {
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 82) DRM_LSPCON_MODE_INVALID,
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 83) DRM_LSPCON_MODE_LS,
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 84) DRM_LSPCON_MODE_PCON,
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 85) };
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 86)
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 87) /**
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 88) * enum drm_dp_dual_mode_type - Type of the DP dual mode adaptor
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 89) * @DRM_DP_DUAL_MODE_NONE: No DP dual mode adaptor
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 90) * @DRM_DP_DUAL_MODE_UNKNOWN: Could be either none or type 1 DVI adaptor
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 91) * @DRM_DP_DUAL_MODE_TYPE1_DVI: Type 1 DVI adaptor
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 92) * @DRM_DP_DUAL_MODE_TYPE1_HDMI: Type 1 HDMI adaptor
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 93) * @DRM_DP_DUAL_MODE_TYPE2_DVI: Type 2 DVI adaptor
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 94) * @DRM_DP_DUAL_MODE_TYPE2_HDMI: Type 2 HDMI adaptor
613a308159e5d (Jani Nikula 2016-10-19 15:08:04 +0300 95) * @DRM_DP_DUAL_MODE_LSPCON: Level shifter / protocol converter
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 96) */
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 97) enum drm_dp_dual_mode_type {
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 98) DRM_DP_DUAL_MODE_NONE,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 99) DRM_DP_DUAL_MODE_UNKNOWN,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 100) DRM_DP_DUAL_MODE_TYPE1_DVI,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 101) DRM_DP_DUAL_MODE_TYPE1_HDMI,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 102) DRM_DP_DUAL_MODE_TYPE2_DVI,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 103) DRM_DP_DUAL_MODE_TYPE2_HDMI,
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 104) DRM_DP_DUAL_MODE_LSPCON,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 105) };
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 106)
92ea222015f17 (Lyude Paul 2021-04-23 14:43:00 -0400 107) enum drm_dp_dual_mode_type
92ea222015f17 (Lyude Paul 2021-04-23 14:43:00 -0400 108) drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter *adapter);
a117f3de3b3aa (Lyude Paul 2021-04-23 14:43:02 -0400 109) int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum drm_dp_dual_mode_type type,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 110) struct i2c_adapter *adapter);
739624d86cb9f (Lyude Paul 2021-04-23 14:43:03 -0400 111) int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 112) struct i2c_adapter *adapter, bool *enabled);
c235509ad740e (Lyude Paul 2021-04-23 14:43:01 -0400 113) int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type,
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 114) struct i2c_adapter *adapter, bool enable);
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 115) const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type);
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 116)
318fbd7dfedd6 (Lyude Paul 2021-04-23 14:43:04 -0400 117) int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter *adapter,
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 118) enum drm_lspcon_mode *current_mode);
318fbd7dfedd6 (Lyude Paul 2021-04-23 14:43:04 -0400 119) int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter *adapter,
056996b956863 (Shashank Sharma 2016-10-17 21:34:37 +0530 120) enum drm_lspcon_mode reqd_mode);
ede53344dbfd1 (Ville Syrjälä 2016-05-06 16:46:52 +0300 121) #endif
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