2874c5fd28426 (Thomas Gleixner 2019-05-27 08:55:01 +0200 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 2) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 3) * Copyright 2017 IBM Corp.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 4) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 5)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 6) #ifndef _MISC_CXLLIB_H
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 7) #define _MISC_CXLLIB_H
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 8)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 9) #include <linux/pci.h>
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 10) #include <asm/reg.h>
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 11)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 12) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 13) * cxl driver exports a in-kernel 'library' API which can be called by
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 14) * other drivers to help interacting with an IBM XSL.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 15) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 16)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 17) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 18) * tells whether capi is supported on the PCIe slot where the
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 19) * device is seated
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 20) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 21) * Input:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 22) * dev: device whose slot needs to be checked
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 23) * flags: 0 for the time being
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 24) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 25) bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 26)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 27)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 28) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 29) * Returns the configuration parameters to be used by the XSL or device
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 30) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 31) * Input:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 32) * dev: device, used to find PHB
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 33) * Output:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 34) * struct cxllib_xsl_config:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 35) * version
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 36) * capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 37) * capi BAR size
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 38) * data send control (XSL_DSNCTL)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 39) * dummy read address (XSL_DRA)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 40) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 41) #define CXL_XSL_CONFIG_VERSION1 1
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 42) struct cxllib_xsl_config {
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 43) u32 version; /* format version for register encoding */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 44) u32 log_bar_size;/* log size of the capi_window */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 45) u64 bar_addr; /* address of the start of capi window */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 46) u64 dsnctl; /* matches definition of XSL_DSNCTL */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 47) u64 dra; /* real address that can be used for dummy read */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 48) };
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 49)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 50) int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 51)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 52)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 53) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 54) * Activate capi for the pci host bridge associated with the device.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 55) * Can be extended to deactivate once we know how to do it.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 56) * Device must be ready to accept messages from the CAPP unit and
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 57) * respond accordingly (TLB invalidates, ...)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 58) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 59) * PHB is switched to capi mode through calls to skiboot.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 60) * CAPP snooping is activated
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 61) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 62) * Input:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 63) * dev: device whose PHB should switch mode
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 64) * mode: mode to switch to i.e. CAPI or PCI
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 65) * flags: options related to the mode
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 66) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 67) enum cxllib_mode {
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 68) CXL_MODE_CXL,
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 69) CXL_MODE_PCI,
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 70) };
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 71)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 72) #define CXL_MODE_NO_DMA 0
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 73) #define CXL_MODE_DMA_TVT0 1
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 74) #define CXL_MODE_DMA_TVT1 2
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 75)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 76) int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 77) unsigned long flags);
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 78)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 79)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 80) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 81) * Set the device for capi DMA.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 82) * Define its dma_ops and dma offset so that allocations will be using TVT#1
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 83) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 84) * Input:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 85) * dev: device to set
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 86) * flags: options. CXL_MODE_DMA_TVT1 should be used
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 87) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 88) int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 89)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 90)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 91) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 92) * Get the Process Element structure for the given thread
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 93) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 94) * Input:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 95) * task: task_struct for the context of the translation
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 96) * translation_mode: whether addresses should be translated
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 97) * Output:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 98) * attr: attributes to fill up the Process Element structure from CAIA
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 99) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 100) struct cxllib_pe_attributes {
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 101) u64 sr;
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 102) u32 lpid;
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 103) u32 tid;
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 104) u32 pid;
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 105) };
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 106) #define CXL_TRANSLATED_MODE 0
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 107) #define CXL_REAL_MODE 1
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 108)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 109) int cxllib_get_PE_attributes(struct task_struct *task,
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 110) unsigned long translation_mode, struct cxllib_pe_attributes *attr);
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 111)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 112)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 113) /*
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 114) * Handle memory fault.
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 115) * Fault in all the pages of the specified buffer for the permissions
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 116) * provided in ‘flags’
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 117) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 118) * Shouldn't be called from interrupt context
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 119) *
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 120) * Input:
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 121) * mm: struct mm for the thread faulting the pages
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 122) * addr: base address of the buffer to page in
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 123) * size: size of the buffer to page in
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 124) * flags: permission requested (DSISR_ISSTORE...)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 125) */
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 126) int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 127)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 128)
3ced8d7300632 (Christophe Lombard 2017-06-22 15:07:27 +0200 129) #endif /* _MISC_CXLLIB_H */
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