280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 1) // SPDX-License-Identifier: GPL-2.0+
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 2) // Copyright 2017 IBM Corp.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 3) #ifndef _MISC_OCXL_H_
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 4) #define _MISC_OCXL_H_
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 5)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 6) #include <linux/pci.h>
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 7)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 8) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 9) * Opencapi drivers all need some common facilities, like parsing the
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 10) * device configuration space, adding a Process Element to the Shared
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 11) * Process Area, etc...
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 12) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 13) * The ocxl module provides a kernel API, to allow other drivers to
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 14) * reuse common code. A bit like a in-kernel library.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 15) */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 16)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 17) #define OCXL_AFU_NAME_SZ (24+1) /* add 1 for NULL termination */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 18)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 19)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 20) struct ocxl_afu_config {
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 21) u8 idx;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 22) int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 23) char name[OCXL_AFU_NAME_SZ];
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 24) u8 version_major;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 25) u8 version_minor;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 26) u8 afuc_type;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 27) u8 afum_type;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 28) u8 profile;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 29) u8 global_mmio_bar; /* global MMIO area */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 30) u64 global_mmio_offset;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 31) u32 global_mmio_size;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 32) u8 pp_mmio_bar; /* per-process MMIO area */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 33) u64 pp_mmio_offset;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 34) u32 pp_mmio_stride;
73a2b047c8104 (Alastair D'Silva 2019-06-05 13:15:45 +0200 35) u64 lpc_mem_offset;
73a2b047c8104 (Alastair D'Silva 2019-06-05 13:15:45 +0200 36) u64 lpc_mem_size;
73a2b047c8104 (Alastair D'Silva 2019-06-05 13:15:45 +0200 37) u64 special_purpose_mem_offset;
73a2b047c8104 (Alastair D'Silva 2019-06-05 13:15:45 +0200 38) u64 special_purpose_mem_size;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 39) u8 pasid_supported_log;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 40) u16 actag_supported;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 41) };
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 42)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 43) struct ocxl_fn_config {
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 44) int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 45) int dvsec_function_pos; /* offset of the Function DVSEC */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 46) int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 47) s8 max_pasid_log;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 48) s8 max_afu_index;
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 49) };
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 50)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 51) enum ocxl_endian {
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 52) OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 53) OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 54) OCXL_HOST_ENDIAN = 2, /**< AFU data is the same endianness as the host */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 55) };
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 56)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 57) // These are opaque outside the ocxl driver
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 58) struct ocxl_afu;
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 59) struct ocxl_fn;
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 60) struct ocxl_context;
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 61)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 62) // Device detection & initialisation
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 63)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 64) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 65) * ocxl_function_open() - Open an OpenCAPI function on an OpenCAPI device
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 66) * @dev: The PCI device that contains the function
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 67) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 68) * Returns an opaque pointer to the function, or an error pointer (check with IS_ERR)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 69) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 70) struct ocxl_fn *ocxl_function_open(struct pci_dev *dev);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 71)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 72) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 73) * ocxl_function_afu_list() - Get the list of AFUs associated with a PCI function device
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 74) * Returns a list of struct ocxl_afu *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 75) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 76) * @fn: The OpenCAPI function containing the AFUs
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 77) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 78) struct list_head *ocxl_function_afu_list(struct ocxl_fn *fn);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 79)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 80) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 81) * ocxl_function_fetch_afu() - Fetch an AFU instance from an OpenCAPI function
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 82) * @fn: The OpenCAPI function to get the AFU from
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 83) * @afu_idx: The index of the AFU to get
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 84) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 85) * If successful, the AFU should be released with ocxl_afu_put()
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 86) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 87) * Returns a pointer to the AFU, or NULL on error
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 88) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 89) struct ocxl_afu *ocxl_function_fetch_afu(struct ocxl_fn *fn, u8 afu_idx);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 90)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 91) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 92) * ocxl_afu_get() - Take a reference to an AFU
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 93) * @afu: The AFU to increment the reference count on
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 94) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 95) void ocxl_afu_get(struct ocxl_afu *afu);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 96)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 97) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 98) * ocxl_afu_put() - Release a reference to an AFU
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 99) * @afu: The AFU to decrement the reference count on
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 100) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 101) void ocxl_afu_put(struct ocxl_afu *afu);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 102)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 103)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 104) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 105) * ocxl_function_config() - Get the configuration information for an OpenCAPI function
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 106) * @fn: The OpenCAPI function to get the config for
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 107) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 108) * Returns the function config, or NULL on error
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 109) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 110) const struct ocxl_fn_config *ocxl_function_config(struct ocxl_fn *fn);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 111)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 112) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 113) * ocxl_function_close() - Close an OpenCAPI function
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 114) * This will free any AFUs previously retrieved from the function, and
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 115) * detach and associated contexts. The contexts must by freed by the caller.
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 116) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 117) * @fn: The OpenCAPI function to close
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 118) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 119) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 120) void ocxl_function_close(struct ocxl_fn *fn);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 121)
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 122) // Context allocation
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 123)
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 124) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 125) * ocxl_context_alloc() - Allocate an OpenCAPI context
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 126) * @context: The OpenCAPI context to allocate, must be freed with ocxl_context_free
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 127) * @afu: The AFU the context belongs to
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 128) * @mapping: The mapping to unmap when the context is closed (may be NULL)
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 129) */
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 130) int ocxl_context_alloc(struct ocxl_context **context, struct ocxl_afu *afu,
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 131) struct address_space *mapping);
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 132)
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 133) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 134) * ocxl_context_free() - Free an OpenCAPI context
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 135) * @ctx: The OpenCAPI context to free
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 136) */
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 137) void ocxl_context_free(struct ocxl_context *ctx);
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 138)
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 139) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 140) * ocxl_context_attach() - Grant access to an MM to an OpenCAPI context
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 141) * @ctx: The OpenCAPI context to attach
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 142) * @amr: The value of the AMR register to restrict access
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 143) * @mm: The mm to attach to the context
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 144) *
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 145) * Returns 0 on success, negative on failure
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 146) */
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 147) int ocxl_context_attach(struct ocxl_context *ctx, u64 amr,
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 148) struct mm_struct *mm);
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 149)
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 150) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 151) * ocxl_context_detach() - Detach an MM from an OpenCAPI context
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 152) * @ctx: The OpenCAPI context to attach
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 153) *
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 154) * Returns 0 on success, negative on failure
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 155) */
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 156) int ocxl_context_detach(struct ocxl_context *ctx);
b9721d275cc2c (Alastair D'Silva 2019-03-27 16:31:33 +1100 157)
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 158) // AFU IRQs
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 159)
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 160) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 161) * ocxl_afu_irq_alloc() - Allocate an IRQ associated with an AFU context
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 162) * @ctx: the AFU context
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 163) * @irq_id: out, the IRQ ID
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 164) *
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 165) * Returns 0 on success, negative on failure
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 166) */
c75d42e4c768c (Alastair D'Silva 2020-04-15 11:23:42 +1000 167) int ocxl_afu_irq_alloc(struct ocxl_context *ctx, int *irq_id);
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 168)
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 169) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 170) * ocxl_afu_irq_free() - Frees an IRQ associated with an AFU context
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 171) * @ctx: the AFU context
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 172) * @irq_id: the IRQ ID
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 173) *
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 174) * Returns 0 on success, negative on failure
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 175) */
c75d42e4c768c (Alastair D'Silva 2020-04-15 11:23:42 +1000 176) int ocxl_afu_irq_free(struct ocxl_context *ctx, int irq_id);
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 177)
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 178) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 179) * ocxl_afu_irq_get_addr() - Gets the address of the trigger page for an IRQ
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 180) * This can then be provided to an AFU which will write to that
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 181) * page to trigger the IRQ.
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 182) * @ctx: The AFU context that the IRQ is associated with
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 183) * @irq_id: The IRQ ID
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 184) *
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 185) * returns the trigger page address, or 0 if the IRQ is not valid
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 186) */
c75d42e4c768c (Alastair D'Silva 2020-04-15 11:23:42 +1000 187) u64 ocxl_afu_irq_get_addr(struct ocxl_context *ctx, int irq_id);
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 188)
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 189) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 190) * ocxl_irq_set_handler() - Provide a callback to be called when an IRQ is triggered
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 191) * @ctx: The AFU context that the IRQ is associated with
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 192) * @irq_id: The IRQ ID
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 193) * @handler: the callback to be called when the IRQ is triggered
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 194) * @free_private: the callback to be called when the IRQ is freed (may be NULL)
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 195) * @private: Private data to be passed to the callbacks
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 196) *
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 197) * Returns 0 on success, negative on failure
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 198) */
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 199) int ocxl_irq_set_handler(struct ocxl_context *ctx, int irq_id,
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 200) irqreturn_t (*handler)(void *private),
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 201) void (*free_private)(void *private),
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 202) void *private);
060146614643d (Alastair D'Silva 2019-03-27 16:31:35 +1100 203)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 204) // AFU Metadata
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 205)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 206) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 207) * ocxl_afu_config() - Get a pointer to the config for an AFU
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 208) * @afu: a pointer to the AFU to get the config for
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 209) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 210) * Returns a pointer to the AFU config
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 211) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 212) struct ocxl_afu_config *ocxl_afu_config(struct ocxl_afu *afu);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 213)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 214) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 215) * ocxl_afu_set_private() - Assign opaque hardware specific information to an OpenCAPI AFU.
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 216) * @afu: The OpenCAPI AFU
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 217) * @private: the opaque hardware specific information to assign to the driver
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 218) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 219) void ocxl_afu_set_private(struct ocxl_afu *afu, void *private);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 220)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 221) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 222) * ocxl_afu_get_private() - Fetch the hardware specific information associated with
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 223) * an external OpenCAPI AFU. This may be consumed by an external OpenCAPI driver.
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 224) * @afu: The OpenCAPI AFU
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 225) *
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 226) * Returns the opaque pointer associated with the device, or NULL if not set
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 227) */
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 228) void *ocxl_afu_get_private(struct ocxl_afu *afu);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 229)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 230) // Global MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 231) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 232) * ocxl_global_mmio_read32() - Read a 32 bit value from global MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 233) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 234) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 235) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 236) * @val: returns the value
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 237) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 238) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 239) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 240) int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 241) enum ocxl_endian endian, u32 *val);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 242)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 243) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 244) * ocxl_global_mmio_read64() - Read a 64 bit value from global MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 245) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 246) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 247) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 248) * @val: returns the value
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 249) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 250) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 251) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 252) int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 253) enum ocxl_endian endian, u64 *val);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 254)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 255) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 256) * ocxl_global_mmio_write32() - Write a 32 bit value to global MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 257) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 258) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 259) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 260) * @val: The value to write
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 261) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 262) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 263) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 264) int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 265) enum ocxl_endian endian, u32 val);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 266)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 267) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 268) * ocxl_global_mmio_write64() - Write a 64 bit value to global MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 269) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 270) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 271) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 272) * @val: The value to write
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 273) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 274) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 275) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 276) int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 277) enum ocxl_endian endian, u64 val);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 278)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 279) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 280) * ocxl_global_mmio_set32() - Set bits in a 32 bit global MMIO register
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 281) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 282) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 283) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 284) * @mask: a mask of the bits to set
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 285) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 286) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 287) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 288) int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 289) enum ocxl_endian endian, u32 mask);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 290)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 291) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 292) * ocxl_global_mmio_set64() - Set bits in a 64 bit global MMIO register
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 293) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 294) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 295) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 296) * @mask: a mask of the bits to set
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 297) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 298) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 299) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 300) int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 301) enum ocxl_endian endian, u64 mask);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 302)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 303) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 304) * ocxl_global_mmio_clear32() - Set bits in a 32 bit global MMIO register
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 305) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 306) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 307) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 308) * @mask: a mask of the bits to set
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 309) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 310) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 311) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 312) int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 313) enum ocxl_endian endian, u32 mask);
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 314)
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 315) /**
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 316) * ocxl_global_mmio_clear64() - Set bits in a 64 bit global MMIO register
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 317) * @afu: The AFU
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 318) * @offset: The Offset from the start of MMIO
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 319) * @endian: the endianness that the MMIO data is in
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 320) * @mask: a mask of the bits to set
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 321) *
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 322) * Returns 0 for success, negative on error
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 323) */
7e462c2a8a6d0 (Alastair D'Silva 2019-03-27 16:31:36 +1100 324) int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset,
3591538a31af3 (Alastair D'Silva 2020-04-15 11:23:43 +1000 325) enum ocxl_endian endian, u64 mask);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 326)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 327) // Functions left here are for compatibility with the cxlflash driver
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 328)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 329) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 330) * Read the configuration space of a function for the AFU specified by
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 331) * the index 'afu_idx'. Fills in a ocxl_afu_config structure
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 332) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 333) int ocxl_config_read_afu(struct pci_dev *dev,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 334) struct ocxl_fn_config *fn,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 335) struct ocxl_afu_config *afu,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 336) u8 afu_idx);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 337)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 338) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 339) * Tell an AFU, by writing in the configuration space, the PASIDs that
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 340) * it can use. Range starts at 'pasid_base' and its size is a multiple
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 341) * of 2
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 342) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 343) * 'afu_control_offset' is the offset of the AFU control DVSEC which
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 344) * can be found in the function configuration
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 345) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 346) void ocxl_config_set_afu_pasid(struct pci_dev *dev,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 347) int afu_control_offset,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 348) int pasid_base, u32 pasid_count_log);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 349)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 350) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 351) * Get the actag configuration for the function:
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 352) * 'base' is the first actag value that can be used.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 353) * 'enabled' it the number of actags available, starting from base.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 354) * 'supported' is the total number of actags desired by all the AFUs
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 355) * of the function.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 356) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 357) int ocxl_config_get_actag_info(struct pci_dev *dev,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 358) u16 *base, u16 *enabled, u16 *supported);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 359)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 360) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 361) * Tell a function, by writing in the configuration space, the actags
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 362) * it can use.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 363) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 364) * 'func_offset' is the offset of the Function DVSEC that can found in
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 365) * the function configuration
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 366) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 367) void ocxl_config_set_actag(struct pci_dev *dev, int func_offset,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 368) u32 actag_base, u32 actag_count);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 369)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 370) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 371) * Tell an AFU, by writing in the configuration space, the actags it
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 372) * can use.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 373) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 374) * 'afu_control_offset' is the offset of the AFU control DVSEC for the
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 375) * desired AFU. It can be found in the AFU configuration
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 376) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 377) void ocxl_config_set_afu_actag(struct pci_dev *dev,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 378) int afu_control_offset,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 379) int actag_base, int actag_count);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 380)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 381) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 382) * Enable/disable an AFU, by writing in the configuration space.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 383) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 384) * 'afu_control_offset' is the offset of the AFU control DVSEC for the
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 385) * desired AFU. It can be found in the AFU configuration
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 386) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 387) void ocxl_config_set_afu_state(struct pci_dev *dev,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 388) int afu_control_offset, int enable);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 389)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 390) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 391) * Set the Transaction Layer configuration in the configuration space.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 392) * Only needed for function 0.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 393) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 394) * It queries the host TL capabilities, find some common ground
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 395) * between the host and device, and set the Transaction Layer on both
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 396) * accordingly.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 397) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 398) int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 399)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 400) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 401) * Request an AFU to terminate a PASID.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 402) * Will return once the AFU has acked the request, or an error in case
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 403) * of timeout.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 404) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 405) * The hardware can only terminate one PASID at a time, so caller must
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 406) * guarantee some kind of serialization.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 407) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 408) * 'afu_control_offset' is the offset of the AFU control DVSEC for the
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 409) * desired AFU. It can be found in the AFU configuration
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 410) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 411) int ocxl_config_terminate_pasid(struct pci_dev *dev,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 412) int afu_control_offset, int pasid);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 413)
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 414) /*
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 415) * Read the configuration space of a function and fill in a
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 416) * ocxl_fn_config structure with all the function details
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 417) */
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 418) int ocxl_config_read_function(struct pci_dev *dev,
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 419) struct ocxl_fn_config *fn);
75ca758adbafc (Alastair D'Silva 2019-03-27 16:31:32 +1100 420)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 421) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 422) * Set up the opencapi link for the function.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 423) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 424) * When called for the first time for a link, it sets up the Shared
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 425) * Process Area for the link and the interrupt handler to process
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 426) * translation faults.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 427) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 428) * Returns a 'link handle' that should be used for further calls for
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 429) * the link
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 430) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 431) int ocxl_link_setup(struct pci_dev *dev, int PE_mask,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 432) void **link_handle);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 433)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 434) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 435) * Remove the association between the function and its link.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 436) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 437) void ocxl_link_release(struct pci_dev *dev, void *link_handle);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 438)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 439) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 440) * Add a Process Element to the Shared Process Area for a link.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 441) * The process is defined by its PASID, pid, tid and its mm_struct.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 442) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 443) * 'xsl_err_cb' is an optional callback if the driver wants to be
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 444) * notified when the translation fault interrupt handler detects an
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 445) * address error.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 446) * 'xsl_err_data' is an argument passed to the above callback, if
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 447) * defined
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 448) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 449) int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
d731feea00c7c (Christophe Lombard 2020-11-25 16:50:11 +0100 450) u64 amr, u16 bdf, struct mm_struct *mm,
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 451) void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 452) void *xsl_err_data);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 453)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 454) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 455) * Remove a Process Element from the Shared Process Area for a link
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 456) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 457) int ocxl_link_remove_pe(void *link_handle, int pasid);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 458)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 459) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 460) * Allocate an AFU interrupt associated to the link.
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 461) *
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 462) * 'hw_irq' is the hardware interrupt number
dde6f18a8779d (Frederic Barrat 2020-04-03 17:38:37 +0200 463) */
dde6f18a8779d (Frederic Barrat 2020-04-03 17:38:37 +0200 464) int ocxl_link_irq_alloc(void *link_handle, int *hw_irq);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 465)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 466) /*
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 467) * Free a previously allocated AFU interrupt
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 468) */
53e3e74530626 (Alastair D'Silva 2019-03-25 16:34:54 +1100 469) void ocxl_link_free_irq(void *link_handle, int hw_irq);
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 470)
280b983ce2b87 (Frederic Barrat 2018-01-23 12:31:43 +0100 471) #endif /* _MISC_OCXL_H_ */
VisionFive2 Linux kernel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
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