VisionFive2 Linux kernel

StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

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author: david.li <david.li@starfivetech.com> 2022-01-05 11:07:47 +0800 committer: david.li <david.li@starfivetech.com> 2022-01-05 11:07:47 +0800 commit: e229e317ec7043a7b0da73f09c08d9cd4a0e9647 parent: 1bb4e7021ca586c0a22684c4b4e7fd0c9c26fde6
Commit Summary:
[v4l2] [add vin path]
Diffstat:
1 file changed, 17 insertions, 5 deletions
diff --git a/include/video/stf-vin.h b/include/video/stf-vin.h
index 8c323ae132f0..405cfc6ad5a6 100755
--- a/include/video/stf-vin.h
+++ b/include/video/stf-vin.h
@@ -148,6 +148,8 @@
 
 //sys control REG DEFINE
 #define SYSCONSAIF_SYSCFG_0						0X0
+#define U0_VIN_SCFG_SRAM_CONFIG     (BIT(0) | BIT(1))
+
 #define SYSCONSAIF_SYSCFG_4			0x4
 #define U0_VIN_CNFG_AXIRD_END_ADDR 0xffffffff
 #define SYSCONSAIF_SYSCFG_8			0x8
@@ -163,16 +165,26 @@
 #define U0_VIN_CNFG_AXIWR0_EN		BIT(4)
 #define U0_VIN_CNFG_AXIWR0_CHANNEL_SEL (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define SYSCONSAIF_SYSCFG_24		0x18
+#define U0_VIN_CNFG_AXIWR0_END_ADDR 0xFFFFFFFF
+
 #define SYSCONSAIF_SYSCFG_28		0x1c
-#define UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL (BIT(15 | BIT(16)))
+#define U0_VIN_CNFG_AXIWR0_INTR_CLEAN BIT(0)
+#define U0_VIN_CNFG_AXIWR0_MASK		BIT(1)
+#define U0_VIN_CNFG_AXIWR0_PIX_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
+#define U0_VIN_CNFG_AXIWR0_PIX_CT (BIT(13) | BIT(14))
+#define UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL (BIT(15) | BIT(16))
 #define SYSCONSAIF_SYSCFG_32		0x20
 
 #define SYSCONSAIF_SYSCFG_36			0x24
+#define UO_VIN_CNFG_COLOR_BAR_EN	BIT(0)
 #define U0_VIN_CNFG_DVP_HS_POS		(0x1<<1)
-#define U0_VIN_CNFG_DVP_SWAP_EN		2
+#define U0_VIN_CNFG_DVP_SWAP_EN		BIT(2)
 #define U0_VIN_CNFG_DVP_VS_POS		(0x1<<3)
-#define U0_VIN_CNFG_GEN_EN_AXIRD	4
-#define U0_VIN_CNFG_ISP_DVP_EN0		5
+#define U0_VIN_CNFG_GEN_EN_AXIRD	BIT(4)
+#define U0_VIN_CNFG_ISP_DVP_EN0		BIT(5)
+#define U0_VIN_CNFG_MIPI_BYTE_EN_ISP0	(BIT(6) |BIT(7))
+#define U0_VIN_CNFG_P_I_MIPI_CHANNEL_SEL0	(BIT(8) |BIT(9) | BIT(10) | BIT(11))
+#define U0_VIN_CNFG_P_I_MIPI_HEADER_EN0 BIT(12)
 
 #define U0_VIN_CNFG_PIX_NUM			(0x1<<13 | 0x1<<14 | 0x1<<15 | 0x1<<16)
 #define U0_VIN_CNFG_AXIRD_AXI_CNT_END	(BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13))
@@ -185,7 +197,7 @@
 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_CT (BIT(13) | BIT(14))
 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
 #define U0_VIN_CNFG_AXIWR0_PIXEL_HITH_BIT_SEL (BIT(15) | BIT(16))
-#define U0_VIN_CNFG_AXIWR0_END_ADDR 0xFFFFFFFF
+
 #define SYSCTRL_REG4	            0x10
 #define SYSCTRL_DPHY_CTRL	        0x14
 #define SYSCTRL_VIN_AXI_CTRL	    0x18