author: jianlong.huang <jianlong.huang@starfivetech.com> 2022-03-24 09:10:54 +0000
committer: jianlong.huang <jianlong.huang@starfivetech.com> 2022-03-24 09:10:54 +0000
commit: 9e388645b2655e030a6906827c4cf9a805874e54
parent: 5bb5438e50fe2b9f9775c2a26179f3a95a37d5bb
Commit Summary:
Diffstat:
1 file changed, 10 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 5b233f74bfc5..d531c6c12951 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -672,8 +672,16 @@
compatible = "cm,codaj12-jpu-1";
reg = <0x0 0x11900000 0x0 0x300>;
reg-names = "control";
- clocks = <&clkgen JH7100_CLK_JPEG_APB>;
- clock-names = "jpege";
+ clocks = <&clkgen JH7100_CLK_JPEG_AXI>,
+ <&clkgen JH7100_CLK_JPEG_CCLK>,
+ <&clkgen JH7100_CLK_JPEG_APB>,
+ <&clkgen JH7100_CLK_VDECBRG_MAIN>,
+ <&clkgen JH7100_CLK_JPCGC300_MAIN>;
+ clock-names = "jpeg_axi", "jpeg_cclk", "jpeg_apb", "vdecbrg_main", "jpcgc300_main";
+ resets = <&rstgen JH7100_RSTN_JPEG_AXI>,
+ <&rstgen JH7100_RSTN_JPEG_CCLK>,
+ <&rstgen JH7100_RSTN_JPEG_APB>;
+ reset-names = "jpeg_axi", "jpeg_cclk", "jpeg_apb";
interrupts = <24>;
memory-region = <&jpu_reserved>;
};