author: Tom <support@vamrs.com> 2021-02-13 22:25:17 +0800
committer: Emil Renner Berthing <kernel@esmil.dk> 2022-06-01 23:15:01 +0200
commit: d27be303d65fb47a3943e297e054364488c24201
parent: 3878532aa9d1de78fdac44265cc69e0f4c43f267
Commit Summary:
Diffstat:
3 files changed, 49 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 09cc98266d30..15e5b36c17b8 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -277,6 +277,44 @@ static int plic_starting_cpu(unsigned int cpu)
return 0;
}
+#if IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+#ifdef CONFIG_SOC_STARFIVE
+#define SIFIVE_L2_MAX_ECCINTR 4
+#else
+#define SIFIVE_L2_MAX_ECCINTR 3
+#endif
+static const struct of_device_id sifive_l2_ids[] = {
+ { .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "starfive,ccache0" },
+ { /* end of table */ },
+};
+
+static void sifive_l2_irq_disable(struct plic_handler *handler)
+{
+ int i, irq;
+ struct of_phandle_args oirq;
+
+ struct device_node *np = of_find_matching_node(NULL, sifive_l2_ids);
+ if (!np) {
+ pr_err("Can't get L2 cache device node.\n");
+ return;
+ }
+
+ for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
+ if (!of_irq_parse_one(np, i, &oirq)) {
+ irq = *oirq.args;
+ if (irq) {
+ pr_info("disable L2 cache irq %d in plic\n", irq);
+ plic_toggle(handler, irq, 0);
+ continue;
+ }
+ }
+ pr_err("Can't get L2 cache irq(#%d).\n", i);
+ }
+}
+#endif
+
+
static int __init plic_init(struct device_node *node,
struct device_node *parent)
{
@@ -370,6 +408,9 @@ static int __init plic_init(struct device_node *node,
done:
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
plic_toggle(handler, hwirq, 0);
+#if IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
+ sifive_l2_irq_disable(handler);
+#endif
nr_handlers++;
}
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 4d0fdab56e81..6f8556df6295 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -22,4 +22,8 @@ config SIFIVE_L2_FLUSH_SIZE
endif # SIFIVE_L2_FLUSH
+config SIFIVE_L2_IRQ_DISABLE
+ bool "Disable Level 2 Cache Controller interrupts"
+ default y if SOC_STARFIVE
+
endif
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 5052d24225c2..de323897a233 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -41,7 +41,9 @@
#define SIFIVE_L2_FLUSH64_LINE_LEN 64
static void __iomem *l2_base = NULL;
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
+#endif
static struct riscv_cacheinfo_ops l2_cache_ops;
enum {
@@ -189,6 +191,7 @@ static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_le
return NULL;
}
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
static irqreturn_t l2_int_handler(int irq, void *device)
{
unsigned int add_h, add_l;
@@ -232,12 +235,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
return IRQ_HANDLED;
}
+#endif
static int __init sifive_l2_init(void)
{
struct device_node *np;
struct resource res;
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
int i, rc, intr_num;
+#endif
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -250,6 +256,7 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
+#if !IS_ENABLED(CONFIG_SIFIVE_L2_IRQ_DISABLE)
intr_num = of_property_count_u32_elems(np, "interrupts");
if (!intr_num) {
pr_err("L2CACHE: no interrupts property\n");
@@ -264,6 +271,7 @@ static int __init sifive_l2_init(void)
return rc;
}
}
+#endif
l2_config_read();