VisionFive2 Linux kernel

StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

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author: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-06-19 00:24:56 +0200 committer: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-07-20 20:53:36 +0200 commit: 09cb761c02468914c6527b044aa8a24c6180dc99 parent: 1c7b5a086e4bae0e27c3753e9a8dca6eec577172
Commit Summary:
riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
Diffstat:
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..941ff282244e 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -27,8 +27,10 @@ config ARCH_STARFIVE
 
 config SOC_STARFIVE
 	bool "StarFive SoCs"
+	select DMA_GLOBAL_POOL
 	select PINCTRL
 	select RESET_CONTROLLER
+	select RISCV_NONSTANDARD_CACHE_OPS
 	help
 	  This enables support for StarFive SoC platform hardware.
 
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..504c73f01f14 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -39,6 +39,30 @@
 			label = "ack";
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dma-reserved {
+			reg = <0x0 0xfa000000 0x0 0x1000000>;
+			no-map;
+		};
+
+		linux,dma {
+			compatible = "shared-dma-pool";
+			reg = <0x10 0x7a000000 0x0 0x1000000>;
+			no-map;
+			linux,dma-default;
+		};
+	};
+
+	soc {
+		dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
+			     <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
+			     <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
+	};
 };
 
 &gpio {