author: Xingyu Wu <xingyu.wu@starfivetech.com> 2023-05-09 23:17:22 +0800
committer: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-07-20 20:52:34 +0200
commit: 4c60e4340c3cf9caedf22ccf841945be25535d34
parent: 62813c2d2a3617a289397582b2db3db9f97111ee
Commit Summary:
Diffstat:
1 file changed, 9 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 000447482aca..4218621ea3b9 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -238,5 +238,15 @@
#size-cells = <0>;
status = "disabled";
};
+
+ watchdog@12480000 {
+ compatible = "starfive,jh7100-wdt";
+ reg = <0x0 0x12480000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
+ <&clkgen JH7100_CLK_WDT_CORE>;
+ clock-names = "apb", "core";
+ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
+ <&rstgen JH7100_RSTN_WDT>;
+ };
};
};