author: Geert Uytterhoeven <geert@linux-m68k.org> 2021-11-25 14:21:18 +0100
committer: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-07-20 20:53:36 +0200
commit: 8083c1d25a73fa63eef48efabb439d55aad7aa96
parent: 09cb761c02468914c6527b044aa8a24c6180dc99
Commit Summary:
Diffstat:
1 file changed, 4 insertions, 4 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 725ef0f08a0e..6905e2c67c30 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -146,8 +146,8 @@
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
ccache: cache-controller@2010000 {
@@ -165,8 +165,8 @@
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
- &cpu1_intc 11 &cpu1_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;