author: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-06-20 15:26:12 +0200
committer: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-07-20 20:53:35 +0200
commit: bf2a8959b2e9c8374feb3b22212353ecfd5f4d18
parent: c55af4db5d008e4daf13600321d1d52741b51662
Commit Summary:
Diffstat:
1 file changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..416789c6459b 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -81,6 +81,11 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
+ sifive,cmo-ops:
+ type: boolean
+ description: |
+ Use the cache flushing register for regular CMO operations.
+
allOf:
- $ref: /schemas/cache-controller.yaml#