author: Arnd Bergmann <arnd@arndb.de> 2023-03-27 14:12:57 +0200
committer: Emil Renner Berthing <emil.renner.berthing@canonical.com> 2023-07-20 20:53:34 +0200
commit: f265eaca05edda71e490bc3ec520a5937e32c49d
parent: abd5c5a3d138dfabddff10a30d01d0ef16c45b55
Commit Summary:
Diffstat:
1 file changed, 8 insertions, 7 deletions
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index b3edbb33b621..91a00d09ffad 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -103,10 +103,10 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
switch (dir) {
case DMA_TO_DEVICE:
- /* Flush the dcache for the requested range */
+ /* Write back the dcache for the requested range */
for (cl = addr; cl < addr + size;
cl += cpuinfo->dcache_block_size)
- mtspr(SPR_DCBFR, cl);
+ mtspr(SPR_DCBWR, cl);
break;
case DMA_FROM_DEVICE:
/* Invalidate the dcache for the requested range */
@@ -114,12 +114,13 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBIR, cl);
break;
+ case DMA_BIDIRECTIONAL:
+ /* Flush the dcache for the requested range */
+ for (cl = addr; cl < addr + size;
+ cl += cpuinfo->dcache_block_size)
+ mtspr(SPR_DCBFR, cl);
+ break;
default:
- /*
- * NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
- * flush nor invalidate the cache here as the area will need
- * to be manually synced anyway.
- */
break;
}
}