author: andy.hu <andy.hu@starfivetech.com> 2023-12-06 09:54:47 +0000
committer: andy.hu <andy.hu@starfivetech.com> 2023-12-06 09:54:47 +0000
commit: 8c7b3f31fb546f829bbce9ee52435342314fabbf
parent: 918eb904cfbc79a48552fe4c842938a94fd3c1d5
Commit Summary:
Diffstat:
1 file changed, 1 insertion, 1 deletion
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index d8f62454fd..f3f830f5f3 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -688,7 +688,7 @@
status = "disabled";
};
- i2c5: i2c@12050000 {
+ i2c5: i2c5@12050000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12050000 0x0 0x10000>;
clocks = <&clkgen JH7110_I2C5_CLK_CORE>,